Searched refs:OVF (Results 1 – 3 of 3) sorted by relevance
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 127 // Fake register to represent USR.OVF bit. Artihmetic/saturating instruc-
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 1069 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi); in LowerUADDSUBO() local
1071 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF, in LowerUADDSUBO()
1076 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 1728 SDValue OVF = Lo.getValue(1); in ExpandIntRes_ADDSUB() local
1732 OVF = DAG.getNode(ISD::AND, dl, NVT, DAG.getConstant(1, dl, NVT), OVF); in ExpandIntRes_ADDSUB()
1735 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF); in ExpandIntRes_ADDSUB()
1738 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF); in ExpandIntRes_ADDSUB()
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