Searched refs:ReadAdvance (Results 1 – 11 of 11) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedA53.td | 145 def : ReadAdvance<ReadExtrHi, 0>;
146 def : ReadAdvance<ReadAdrBase, 0>;
147 def : ReadAdvance<ReadVLD, 0>;
152 // ReadAdvance applies to Extended registers as well, even though there is
154 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
178 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
182 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
188 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
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| D | AArch64SchedA57.td | 106 def : ReadAdvance<ReadI, 0>;
107 def : ReadAdvance<ReadISReg, 0>;
108 def : ReadAdvance<ReadIEReg, 0>;
109 def : ReadAdvance<ReadIM, 0>;
110 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
111 def : ReadAdvance<ReadID, 0>;
112 def : ReadAdvance<ReadExtrHi, 0>;
113 def : ReadAdvance<ReadAdrBase, 0>;
114 def : ReadAdvance<ReadVLD, 0>;
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| D | AArch64SchedCyclone.td | 182 def : ReadAdvance<ReadExtrHi, 1>;
631 def : ReadAdvance<ReadVLD, 5>;
858 def : ReadAdvance<ReadI, 0>;
859 def : ReadAdvance<ReadISReg, 0>;
860 def : ReadAdvance<ReadIEReg, 0>;
861 def : ReadAdvance<ReadIM, 0>;
862 def : ReadAdvance<ReadIMA, 0>;
863 def : ReadAdvance<ReadID, 0>;
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| /external/llvm/include/llvm/Target/ |
| D | TargetSchedule.td | 27 // each subtarget, define WriteRes and ReadAdvance to associate
291 // Define values common to ReadAdvance and SchedReadAdvance.
303 // A processor may define a ReadAdvance associated with a SchedRead
308 // A ReadAdvance may be associated with a list of SchedWrites
313 class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []>
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| /external/llvm/utils/TableGen/ |
| D | SubtargetEmitter.cpp | 977 Record *ReadAdvance = in GenSchedClassTables() local
979 if (!ReadAdvance) in GenSchedClassTables()
983 if (ReadAdvance->getValueAsBit("Unsupported")) { in GenSchedClassTables()
987 RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites"); in GenSchedClassTables()
1002 RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles"); in GenSchedClassTables()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMSchedule.td | 38 // ReadAdvance read resources allow us to define "pipeline by-passes" or
55 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
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| D | ARMScheduleSwift.td | 134 def : ReadAdvance<ReadALU, 0>;
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| /external/llvm/lib/Target/X86/ |
| D | X86ScheduleSLM.td | 52 def : ReadAdvance<ReadAfterLd, 3>;
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| D | X86SchedSandyBridge.td | 65 def : ReadAdvance<ReadAfterLd, 4>;
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| D | X86ScheduleBtVer2.td | 70 def : ReadAdvance<ReadAfterLd, 3>;
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| D | X86SchedHaswell.td | 75 def : ReadAdvance<ReadAfterLd, 4>;
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