| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 259 case ISD::SUBE: in selectNode()
264 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in selectNode()
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| D | MipsSEISelDAGToDAG.cpp | 241 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in selectAddESubE()
718 case ISD::SUBE: { in selectNode()
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| D | MipsSEISelLowering.cpp | 143 setTargetDAGCombine(ISD::SUBE); in MipsSETargetLowering()
1081 case ISD::SUBE: in PerformDAGCombine()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 223 ADDE, SUBE, enumerator
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 73 SUBE, // Sub using carry enumerator
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| D | ARMISelLowering.cpp | 744 setOperationAction(ISD::SUBE, MVT::i32, Custom); in ARMTargetLowering()
1133 case ARMISD::SUBE: return "ARMISD::SUBE"; in getTargetNodeName()
6622 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
6882 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
11174 case ARMISD::SUBE: in computeKnownBitsForTargetNode()
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| D | ARMInstrInfo.td | 161 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 234 case ISD::SUBE: return "sube"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 1381 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; in ExpandIntegerResult()
1706 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
1787 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
2912 SDValue LowCmp = DAG.getNode(ISD::SUBE, dl, VTList, LHSLo, RHSLo, Carry); in ExpandIntOp_SETCCE()
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| D | DAGCombiner.cpp | 1366 case ISD::SUBE: return visitSUBE(N); in visit()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 154 ISD::SUBE}) { in WebAssemblyTargetLowering()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 130 setOperationAction(ISD::SUBE, MVT::i64, Expand); in BPFTargetLowering()
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 111 setOperationAction(ISD::SUBE, VT, Expand); in InitAMDILLowering()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1646 setOperationAction(ISD::SUBE, MVT::i8, Expand); in HexagonTargetLowering()
1647 setOperationAction(ISD::SUBE, MVT::i16, Expand); in HexagonTargetLowering()
1648 setOperationAction(ISD::SUBE, MVT::i32, Expand); in HexagonTargetLowering()
1649 setOperationAction(ISD::SUBE, MVT::i64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1566 setOperationAction(ISD::SUBE, MVT::i64, Custom); in SparcTargetLowering()
2836 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
2837 case ISD::SUBE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
2970 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
|
| D | SparcInstrInfo.td | 600 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 392 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 96 setOperationAction(ISD::SUBE, MVT::i32, Expand); in XCoreTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 209 setOperationAction(ISD::SUBE, MVT::i32, Custom); in AArch64TargetLowering()
213 setOperationAction(ISD::SUBE, MVT::i64, Custom); in AArch64TargetLowering()
1748 case ISD::SUBE: in LowerADDC_ADDE_SUBC_SUBE()
2270 case ISD::SUBE: in LowerOperation()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 78 setOperationAction(ISD::SUBE, MVT::i32, Legal); in SITargetLowering()
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| D | R600ISelLowering.cpp | 187 setOperationAction(ISD::SUBE, VT, Expand); in R600TargetLowering()
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| D | AMDGPUISelLowering.cpp | 322 setOperationAction(ISD::SUBE, VT, Expand); in AMDGPUTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 291 setOperationAction(ISD::SUBE, VT, Custom); in X86TargetLowering()
19682 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
20139 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
20216 case ISD::SUBE: in ReplaceNodeResults()
|