Searched refs:Src0RC (Results 1 – 3 of 3) sorted by relevance
/external/llvm/lib/Target/AMDGPU/ |
D | SIFixSGPRCopies.cpp | 357 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; in runOnMachineFunction() local 359 Src0RC = MRI.getRegClass(MI.getOperand(1).getReg()); in runOnMachineFunction() 362 (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) { in runOnMachineFunction()
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D | SIInstrInfo.cpp | 2065 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0); in legalizeOperands() local 2066 if (DstRC != Src0RC) { in legalizeOperands() 2661 const TargetRegisterClass *Src0RC = Src0.isReg() ? in splitScalar64BitUnaryOp() local 2665 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp() 2667 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp() 2678 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp() 2716 const TargetRegisterClass *Src0RC = Src0.isReg() ? in splitScalar64BitBinaryOp() local 2720 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitBinaryOp() 2727 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitBinaryOp() 2741 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitBinaryOp()
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D | SIInstrInfo.td | 1055 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> { 1056 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1 1057 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2 1062 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC, 1070 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, 1074 (ins Src0RC:$src0) 1079 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, 1084 (ins Src0RC:$src0, Src1RC:$src1) 1089 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, 1095 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
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