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Searched refs:SubRegIndices (Results 1 – 18 of 18) sorted by relevance

/external/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp140 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums() local
141 if (!SubRegIndices.empty()) { in runEnums()
143 std::string Namespace = SubRegIndices.front().getNamespace(); in runEnums()
148 for (const auto &Idx : SubRegIndices) in runEnums()
633 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices() local
649 std::distance(SubRegIndices.begin(), SubRegIndices.end()); in emitComposeSubRegIndices()
650 for (const auto &Idx : SubRegIndices) { in emitComposeSubRegIndices()
704 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask() local
709 for (const auto &Idx : SubRegIndices) { in emitComposeSubRegIndexLaneMask()
756 for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) { in emitComposeSubRegIndexLaneMask()
[all …]
DCodeGenRegisters.cpp936 for (auto &Idx : SubRegIndices) in CodeGenRegBank()
1015 SubRegIndices.emplace_back(Name, Namespace, SubRegIndices.size() + 1); in createSubRegIndex()
1016 return &SubRegIndices.back(); in createSubRegIndex()
1023 SubRegIndices.emplace_back(Def, SubRegIndices.size() + 1); in getSubRegIdx()
1024 Idx = &SubRegIndices.back(); in getSubRegIdx()
1172 for (auto &Idx : SubRegIndices) { in computeSubRegLaneMasks()
1193 for (const auto &Idx : SubRegIndices) { in computeSubRegLaneMasks()
1201 for (auto &Idx2 : SubRegIndices) { in computeSubRegLaneMasks()
1254 for (const auto &Idx : SubRegIndices) { in computeSubRegLaneMasks()
1265 for (const auto &SubRegIndex : SubRegIndices) { in computeSubRegLaneMasks()
[all …]
DCodeGenRegisters.h481 std::deque<CodeGenSubRegIndex> SubRegIndices; variable
571 return SubRegIndices; in getSubRegIndices()
/external/llvm/lib/MC/
DMCRegisterInfo.cpp31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg()
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex()
/external/llvm/include/llvm/MC/
DMCRegisterInfo.h112 uint32_t SubRegIndices; member
168 const uint16_t *SubRegIndices; // Pointer to the subreg lookup variable
269 SubRegIndices = SubIndices; in InitMCRegisterInfo()
475 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices; in MCSubRegIndexIterator()
/external/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td66 let SubRegIndices = [subreg_l32, subreg_h32];
73 let SubRegIndices = [subreg_l64, subreg_h64];
180 let SubRegIndices = [subreg_r32];
187 let SubRegIndices = [subreg_l64, subreg_h64];
222 let SubRegIndices = [subreg_r64];
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td39 let SubRegIndices = [sub_32];
56 let SubRegIndices = [sub_64];
71 let SubRegIndices = [sub_64];
79 let SubRegIndices = [sub_64];
88 let SubRegIndices = [sub_128];
193 let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in {
/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.td47 let SubRegIndices = [sub_32];
56 let SubRegIndices = [sub_lo, sub_hi];
62 let SubRegIndices = [sub_lo, sub_hi];
69 let SubRegIndices = [sub_64];
75 let SubRegIndices = [sub_lo, sub_hi];
191 let SubRegIndices = [sub_32] in {
247 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22,
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td96 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
145 let SubRegIndices = [subreg_overflow];
158 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
173 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td77 let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in {
83 let SubRegIndices = [sub_8bit] in {
92 let SubRegIndices = [sub_8bit], CostPerUse = 1 in {
104 let SubRegIndices = [sub_16bit] in {
128 let SubRegIndices = [sub_32bit] in {
213 let SubRegIndices = [sub_xmm] in {
221 let SubRegIndices = [sub_ymm] in {
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td30 let SubRegIndices = [sub0, sub1];
40 let SubRegIndices = [sub0, sub1];
57 let SubRegIndices = [sub0, sub1];
DR600RegisterInfo.td23 let SubRegIndices = [sub0, sub1, sub2, sub3];
32 let SubRegIndices = [sub0, sub1];
/external/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.td48 let SubRegIndices = [subreg_8bit] in {
/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td38 let SubRegIndices = [sub_even, sub_odd];
47 let SubRegIndices = [sub_even, sub_odd];
54 let SubRegIndices = [sub_even64, sub_odd64];
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td89 let SubRegIndices = [sub_32] in {
249 let SubRegIndices = [bsub] in {
284 let SubRegIndices = [hsub] in {
319 let SubRegIndices = [ssub], RegAltNameIndices = [vreg, vlist1] in {
354 let SubRegIndices = [dsub], RegAltNameIndices = [vreg, vlist1] in {
/external/llvm/lib/Target/ARM/
DARMRegisterInfo.td99 let SubRegIndices = [ssub_0, ssub_1] in {
137 let SubRegIndices = [dsub_0, dsub_1] in {
147 let SubRegIndices = [dsub_0, dsub_1] in {
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td80 let SubRegIndices = [sub_lo, sub_hi],
/external/llvm/include/llvm/Target/
DTarget.td96 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
99 list<SubRegIndex> SubRegIndices = [];
266 // let SubRegIndices = [sube, subo] in {
284 // SubRegIndices - N SubRegIndex instances. This provides the names of the
286 list<SubRegIndex> SubRegIndices = Indices;