Searched refs:TGSI_OPCODE_ARL (Results 1 – 14 of 14) sorted by relevance
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_info.c | 40 { 1, 1, 0, 0, 0, 0, COMP, "ARL", TGSI_OPCODE_ARL },
353 case TGSI_OPCODE_ARL: in tgsi_opcode_infer_dst_type()
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| D | tgsi_util.c | 183 case TGSI_OPCODE_ARL: in tgsi_util_get_inst_usage_mask()
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| D | tgsi_exec.c | 3456 case TGSI_OPCODE_ARL: in exec_instruction()
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| /external/mesa3d/src/gallium/include/pipe/ |
| D | p_shader_tokens.h | 258 #define TGSI_OPCODE_ARL 0 macro
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| /external/mesa3d/src/gallium/drivers/r300/ |
| D | r300_tgsi_to_rc.c | 35 case TGSI_OPCODE_ARL: return RC_OPCODE_ARL; in translate_opcode()
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| /external/mesa3d/src/gallium/drivers/nv30/ |
| D | nvfx_vertprog.c | 536 finst->Instruction.Opcode != TGSI_OPCODE_ARL) in nvfx_vertprog_parse_instruction()
542 assert(finst->Instruction.Opcode != TGSI_OPCODE_ARL); in nvfx_vertprog_parse_instruction()
557 case TGSI_OPCODE_ARL: in nvfx_vertprog_parse_instruction()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_setup_tgsi_llvm.c | 1111 bld_base->op_actions[TGSI_OPCODE_ARL].emit = build_tgsi_intrinsic_nomem; in radeon_llvm_context_init()
1112 bld_base->op_actions[TGSI_OPCODE_ARL].intr_name = "llvm.AMDGPU.arl"; in radeon_llvm_context_init()
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_mesa_to_tgsi.c | 531 return TGSI_OPCODE_ARL; in translate_opcode()
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| D | st_glsl_to_tgsi.cpp | 527 if (op == TGSI_OPCODE_ARL || op == TGSI_OPCODE_UARL) in emit()
762 int op = TGSI_OPCODE_ARL; in emit_arl()
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_tgsi_aos.c | 483 case TGSI_OPCODE_ARL: in lp_emit_instruction_aos()
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| D | lp_bld_tgsi_action.c | 1566 bld_base->op_actions[TGSI_OPCODE_ARL].emit = arl_emit_cpu; in lp_set_default_actions_cpu()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_shader.c | 4761 case TGSI_OPCODE_ARL: in tgsi_eg_arl()
4793 case TGSI_OPCODE_ARL: in tgsi_r600_arl()
5234 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
5414 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
5588 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
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| /external/mesa3d/src/gallium/drivers/svga/ |
| D | svga_tgsi_insn.c | 2532 case TGSI_OPCODE_ARL: in svga_emit_instruction()
3244 TGSI_OPCODE_ARL) { in pre_parse_tokens()
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 1813 case TGSI_OPCODE_ARL: in handleInstruction()
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