Searched refs:V5 (Results 1 – 25 of 57) sorted by relevance
123
| /external/llvm/test/CodeGen/Thumb/ |
| D | ldr_ext.ll | 1 ; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s -check-prefix=V5
7 ; V5: ldrb
16 ; V5: ldrh
25 ; V5: ldrb
26 ; V5: lsls
27 ; V5: asrs
37 ; V5: ldrh
38 ; V5: lsls
39 ; V5: asrs
49 ; V5: movs r0, #0
[all …]
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| /external/llvm/unittests/Support/ |
| D | AlignOfTest.cpp | 70 struct V5 : V4, V3 { double z; struct
71 ~V5() override;
77 struct V8 : V5, virtual V6, V7 { double zz;
87 V5::~V5() {} in ~V5()
133 [AlignOf<V5>::Alignment > 0]
173 EXPECT_LE(alignOf<V1>(), alignOf<V5>()); in TEST()
251 EXPECT_EQ(alignOf<V5>(), alignOf<AlignedCharArrayUnion<V5> >()); in TEST()
316 EXPECT_EQ(sizeof(V5), sizeof(AlignedCharArrayUnion<V5>)); in TEST()
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| /external/llvm/test/CodeGen/ARM/ |
| D | MachO-subtypes.ll | 7 ; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5
9 ; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5
11 ; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5
13 ; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5
15 ; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5
61 ; CHECK-V5: CpuSubType: CPU_SUBTYPE_ARM_V5 (0x7)
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| D | pr18364-movw.ll | 1 ; RUN: llc < %s -mtriple=armv5te | FileCheck %s --check-prefix=V5
9 ; V5-NOT: movw
25 ; V5-NOT: movw
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.h | 42 V4, V5, V55, V60 enumerator
90 bool hasV5TOps() const { return getHexagonArchVersion() >= V5; } in hasV5TOps()
91 bool hasV5TOpsOnly() const { return getHexagonArchVersion() == V5; } in hasV5TOpsOnly()
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| D | HexagonRegisterInfo.cpp | 68 case HexagonSubtarget::V5: in getCallerSavedRegs()
88 case HexagonSubtarget::V5: in getCalleeSavedRegs()
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| /external/llvm/test/MC/AArch64/ |
| D | case-insen-reg-names.s | 4 fadd V0.2d, V5.2d, V6.2d
5 fadd v0.2d, V5.2d, v6.2d
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| /external/llvm/test/Transforms/SimplifyCFG/ |
| D | PhiEliminate2.ll | 10 %V5 = sext i16 %V3 to i32 ; <i32> [#uses=1]
13 %V6 = phi i32 [ %V5, %else ], [ %V4, %then ] ; <i32> [#uses=0]
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| /external/clang/test/SemaCXX/ |
| D | MicrosoftExtensions.cpp | 191 __declspec(property(get=GetV, put=SetV)) int V5; member
202 int k = sp.V5; in TestProperty()
203 sp.V5 = k++; in TestProperty()
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| /external/clang/test/Parser/ |
| D | recovery.cpp | 151 enum class EC3 { V0 = 0, V5 = 5 }; // expected-note {{declared here}}
167 …case EC3::V5:: break; // expected-error{{'V5' cannot appear before '::' because it is not a class,…
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | opt-fabs.ll | 2 ; Optimize fabsf to clrbit in V5.
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| D | dsub.ll | 2 ; Check that we generate double precision floating point subtract in V5.
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| D | fadd.ll | 2 ; Check that we generate sp floating point add in V5.
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| D | fsub.ll | 2 ; Check that we generate sp floating point subtract in V5.
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| D | dadd.ll | 2 ; Check that we generate double precision floating point add in V5.
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| D | dmul.ll | 2 ; Check that we generate double precision floating point multiply in V5.
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| D | fmul.ll | 2 ; Check that we generate single precision floating point multiply in V5.
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| D | opt-fneg.ll | 2 ; Optimize fneg to togglebit in V5.
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| D | convertsptoint.ll | 3 ; to 32-bit int value in IEEE complaint mode in V5.
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| D | convertdptoint.ll | 3 ; to 32-bit int value in IEEE complaint mode in V5.
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| D | doubleconvert-ieee-rnd-near.ll | 3 ; to 32-bit int value in IEEE rounding to the nearest mode in V5.
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| D | convertsptoll.ll | 3 ; to 64-bit int value in IEEE complaint mode in V5.
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| D | convertdptoll.ll | 3 ; to 64-bit integer value in IEEE complaint mode in V5.
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| D | fcmp.ll | 2 ; Check that we generate floating point compare in V5
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| /external/llvm/test/MC/ARM/ |
| D | thumb-diagnostics.s | 4 @ RUN: | FileCheck --check-prefix=CHECK-ERRORS-V5 %s
24 @ CHECK-ERRORS-V5: error: instruction variant requires ARMv6 or later
25 @ CHECK-ERRORS-V5: mov r2, r3
26 @ CHECK-ERRORS-V5: ^
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