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Searched refs:VAR1 (Results 1 – 10 of 10) sorted by relevance

/external/llvm/test/Transforms/InstCombine/
Dselect-cmp-cttz-ctlz.ll141 ; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %x, i1 false)
142 ; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = zext i16 [[VAR1]] to i32
154 ; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %x, i1 false)
155 ; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = zext i16 [[VAR1]] to i64
167 ; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 false)
168 ; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = zext i32 [[VAR1]] to i64
180 ; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %x, i1 false)
181 ; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = zext i16 [[VAR1]] to i32
193 ; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %x, i1 false)
194 ; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = zext i16 [[VAR1]] to i64
[all …]
Dvec_shuffle.ll315 ; CHECK-NEXT: [[VAR1:%[a-zA-Z0-9.]+]] = fsub fast <4 x float> %v1, %v2
316 ; CHECK-NEXT: shufflevector <4 x float> [[VAR1]], <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3…
329 ; CHECK: [[VAR1:%[a-zA-Z0-9.]+]] = add <4 x i32> %v1, <i32 4, i32 1, i32 2, i32 3>
330 ; CHECK: [[VAR2:%[a-zA-Z0-9.]+]] = shufflevector <4 x i32> [[VAR1]], <4 x i32> undef, <4 x i32> <i3…
354 ; CHECK: [[VAR1:%[a-zA-Z0-9.]+]] = mul <4 x i32> %v, %v
355 ; CHECK: [[VAR2:%[a-zA-Z0-9.]+]] = shufflevector <4 x i32> [[VAR1]], <4 x i32> undef, <4 x i32> zer…
381 ; CHECK: [[VAR1:%[a-zA-Z0-9.]+]] = mul <8 x i16> %in0, %in1
382 ; CHECK: [[VAR2:%[a-zA-Z0-9.]+]] = shufflevector <8 x i16> [[VAR1]], <8 x i16> undef, <4 x i32> <i3…
/external/clang/test/CodeGenCXX/
Dmangle-local-class-names.cpp19 SSSS VAR1(IVAR1); in FUNC() local
43 SSSS VAR1(IVAR1); in GORF() local
66 SSSS VAR1(x); in OmittingCode() local
/external/llvm/test/Transforms/IndVarSimplify/
Dloop_evaluate_1.ll26 ; CHECK: [[VAR1:%.+]] = add i32 %arg, -11
27 ; CHECK: [[VAR2:%.+]] = lshr i32 [[VAR1]], 1
/external/llvm/test/Transforms/LoopVectorize/
Dstore-shuffle-bug.ll22 ; CHECK: [[VAR1:%[a-zA-Z0-9.]+]] = load <4 x i32>
24 ; CHECK: [[VAR3:%[a-zA-Z0-9]+]] = add nsw <4 x i32> [[VAR2]], [[VAR1]]
/external/llvm/test/CodeGen/Hexagon/
Dextload-combine.ll29 ; CHECK: [[VAR1:r[0-9]+]]{{ *}}={{ *}}memh(##
30 ; CHECK: sxtw([[VAR1]])
/external/pcre/dist/cmake/
DFindPackageHandleStandardArgs.cmake1 # FIND_PACKAGE_HANDLE_STANDARD_ARGS(NAME (DEFAULT_MSG|"Custom failure message") VAR1 ... )
14 # If it is found, the location is reported using the VAR1 argument, so
/external/eigen/bench/btl/cmake/
DFindPackageHandleStandardArgs.cmake1 # FIND_PACKAGE_HANDLE_STANDARD_ARGS(NAME (DEFAULT_MSG|"Custom failure message") VAR1 ... )
16 # If it is found, the location is reported using the VAR1 argument, so
/external/clang/test/CodeGenObjC/
Darc-unoptimized-byref-var.m8 // CHECK-UNOPT: [[X2:%.*]] = getelementptr inbounds [[BYREF_T:%.*]], [[BYREF_T:%.*]]* [[VAR1:%.*]],…
/external/valgrind/drd/tests/
Dtsan_unittest.cpp5758 int VAR1 = 0; variable
5773 void Thread1() { WriteWhileHoldingReaderLock(&VAR1); } in Thread1()
5774 void Thread2() { CorrectWrite(&VAR1); } in Thread2()
5781 VAR1 = 0; in Run()
5783 ANNOTATE_TRACE_MEMORY(&VAR1); in Run()
5786 ANNOTATE_EXPECT_RACE_FOR_TSAN(&VAR1, "test122. TP. ReaderLock-ed while writing"); in Run()