Searched refs:VCGE (Results 1 – 10 of 10) sorted by relevance
| /external/llvm/test/CodeGen/ARM/ |
| D | vfcmp.ll | 28 ; ole is implemented with VCGE
63 ; ugt is implemented with VCGE/VMVN
75 ; ult is implemented with VCGE/VMVN
114 ; uno is implemented with VCGT/VCGE/VORR/VMVN
128 ; ord is implemented with VCGT/VCGE/VORR
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| D | vicmp.ll | 6 ; to VCGT and VCGE. Test all the operand types for not-equal but only sample
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 97 VCGE, // Vector compare greater than or equal. enumerator
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| D | ARMScheduleSwift.td | 555 "VACLE", "VACLT", "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
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| D | ARMISelLowering.cpp | 1157 case ARMISD::VCGE: return "ARMISD::VCGE"; in getTargetNodeName()
4641 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC()
4645 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; in LowerVSETCC()
4662 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1); in LowerVSETCC()
4674 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC()
4712 if (Opc == ARMISD::VCGE) in LowerVSETCC()
4724 case ARMISD::VCGE: in LowerVSETCC()
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| D | ARMScheduleA9.td | 2411 // VSBH/VRSBH/VHSUB/VQSUB/VABD/VCEQ/VCGE/VCGT/VMAX/VMIN/VPMAX/VPMIN/VABDL
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| D | ARMInstrNEON.td | 497 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
4729 // VCGE : Vector Compare Greater Than or Equal
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| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 551 def VCGE : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>;
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| /external/valgrind/none/tests/arm/ |
| D | neon128.stdout.exp | 387 ---- VCGE ----
1844 ---- VCGE #0 ----
3854 ---- VCGE (fp) ----
4117 ---- VCGE (fp) #0 ----
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| D | neon64.stdout.exp | 535 ---- VCGE ----
3088 ---- VCGE #0 ----
5788 ---- VCGE (fp) ----
6247 ---- VCGE (fp) #0 ----
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