Searched refs:ValOp (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 3590 SDValue ValOp = GetWidenedVector(ST->getValue()); in GenWidenVectorStores() local
3595 EVT ValVT = ValOp.getValueType(); in GenWidenVectorStores()
3612 ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, in GenWidenVectorStores()
3629 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp); in GenWidenVectorStores()
3664 SDValue ValOp = GetWidenedVector(ST->getValue()); in GenWidenVectorTruncStores() local
3668 EVT ValVT = ValOp.getValueType(); in GenWidenVectorTruncStores()
3672 assert(StVT.isVector() && ValOp.getValueType().isVector()); in GenWidenVectorTruncStores()
3673 assert(StVT.bitsLT(ValOp.getValueType())); in GenWidenVectorTruncStores()
3683 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, in GenWidenVectorTruncStores()
3696 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, in GenWidenVectorTruncStores()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 1826 MachineOperand &ValOp = MI->getOperand(2); in genStoreUpperHalf() local
1827 BitTracker::RegisterRef RS = ValOp; in genStoreUpperHalf()
1837 ValOp.setReg(H.Reg); in genStoreUpperHalf()
1838 ValOp.setSubReg(H.Sub); in genStoreUpperHalf()
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| D | HexagonSplitDouble.cpp | 611 MachineOperand &ValOp = Load ? MI->getOperand(0) in splitMemRef() local
614 UUPairMap::const_iterator F = PairMap.find(ValOp.getReg()); in splitMemRef()
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| /external/llvm/lib/Transforms/Scalar/ |
| D | SROA.cpp | 756 Value *ValOp = SI.getValueOperand(); in visitStoreInst() local
757 if (ValOp == *U) in visitStoreInst()
763 uint64_t Size = DL.getTypeStoreSize(ValOp->getType()); in visitStoreInst()
781 assert((!SI.isSimple() || ValOp->getType()->isSingleValueType()) && in visitStoreInst()
783 handleLoadOrStore(ValOp->getType(), SI, Offset, Size, SI.isVolatile()); in visitStoreInst()
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