Searched refs:WideVecVT (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 15358 EVT WideVecVT = in LowerExtendedLoad() local
15362 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() && in LowerExtendedLoad()
15366 assert(TLI.isTypeLegal(WideVecVT) && in LowerExtendedLoad()
15397 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res); in LowerExtendedLoad()
15423 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, in LowerExtendedLoad()
15424 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]); in LowerExtendedLoad()
25976 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), in PerformMLOADCombine() local
25978 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); in PerformMLOADCombine()
25981 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0()); in PerformMLOADCombine()
25988 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) && in PerformMLOADCombine()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 9857 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(), in PerformSTORECombine() local
9859 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); in PerformSTORECombine()
9862 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal); in PerformSTORECombine()
9870 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); in PerformSTORECombine()
9872 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec, in PerformSTORECombine()
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