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Searched refs:WriteRes (Results 1 – 13 of 13) sorted by relevance

/external/llvm/lib/Target/X86/
DX86ScheduleSLM.td63 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
67 def : WriteRes<SchedRW.Folded, [MEC_RSV, ExePort]> {
74 def : WriteRes<WriteRMW, [MEC_RSV]>;
76 def : WriteRes<WriteStore, [IEC_RSV01, MEC_RSV]>;
77 def : WriteRes<WriteLoad, [MEC_RSV]> { let Latency = 3; }
78 def : WriteRes<WriteMove, [IEC_RSV01]>;
79 def : WriteRes<WriteZero, []>;
89 def : WriteRes<WriteLEA, [IEC_RSV1]>;
92 def : WriteRes<WriteIDiv, [IEC_RSV01, SMDivider]> {
96 def : WriteRes<WriteIDivLd, [MEC_RSV, IEC_RSV01, SMDivider]> {
[all …]
DX86ScheduleBtVer2.td81 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
85 def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
94 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
98 def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
104 def : WriteRes<WriteRMW, [JSAGU]>;
113 def : WriteRes<WriteIMulH, [JALU1]> {
119 def : WriteRes<WriteIDiv, [JALU1, JDiv]> {
123 def : WriteRes<WriteIDivLd, [JALU1, JLAGU, JDiv]> {
130 def : WriteRes<WriteLEA, [JALU01]>;
143 def : WriteRes<WriteLoad, [JLAGU]> { let Latency = 5; }
[all …]
DX86SchedSandyBridge.td76 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
80 def : WriteRes<SchedRW.Folded, [SBPort23, ExePort]> {
87 def : WriteRes<WriteRMW, [SBPort4]>;
89 def : WriteRes<WriteStore, [SBPort23, SBPort4]>;
90 def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 4; }
91 def : WriteRes<WriteMove, [SBPort015]>;
92 def : WriteRes<WriteZero, []>;
96 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
103 def : WriteRes<WriteLEA, [SBPort15]>;
106 def : WriteRes<WriteIDiv, [SBPort0, SBDivider]> {
[all …]
DX86SchedHaswell.td86 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
90 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> {
97 def : WriteRes<WriteRMW, [HWPort4]>;
101 def : WriteRes<WriteStore, [HWPort237, HWPort4]>;
102 def : WriteRes<WriteLoad, [HWPort23]> { let Latency = 4; }
103 def : WriteRes<WriteMove, [HWPort0156]>;
104 def : WriteRes<WriteZero, []>;
108 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
115 def : WriteRes<WriteLEA, [HWPort15]>;
118 def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> {
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64SchedA53.td57 def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
58 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
59 def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 3; }
60 def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 3; }
61 def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
62 def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 3; }
65 def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; }
66 def : WriteRes<WriteIM64, [A53UnitMAC]> { let Latency = 4; }
69 def : WriteRes<WriteID32, [A53UnitDiv]> { let Latency = 4; }
70 def : WriteRes<WriteID64, [A53UnitDiv]> { let Latency = 4; }
[all …]
DAArch64SchedCyclone.td129 def : WriteRes<WriteImm, [CyUnitI]>;
148 def : WriteRes<WriteI, [CyUnitI]>;
154 def : WriteRes<WriteISReg, [CyUnitIS]> {
162 def : WriteRes<WriteIEReg, [CyUnitIS]> {
169 def : WriteRes<WriteIS, [CyUnitIS]>;
174 def : WriteRes<WriteExtr, [CyUnitIS, CyUnitIS]> {
190 def : WriteRes<WriteIM32, [CyUnitIM]> {
194 def : WriteRes<WriteIM64, [CyUnitIM]> {
205 def : WriteRes<WriteID32, [CyUnitID, CyUnitIntDiv]> {
212 def : WriteRes<WriteID64, [CyUnitID, CyUnitIntDiv]> {
[all …]
DAArch64SchedA57.td61 // defining the aliases precludes the need for mapping them using WriteRes. The
78 def : WriteRes<WriteIM32, [A57UnitM]> { let Latency = 3; }
79 def : WriteRes<WriteIM64, [A57UnitM]> { let Latency = 5; }
99 def : WriteRes<WriteSys, []> { let Latency = 1; }
100 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
101 def : WriteRes<WriteHint, []> { let Latency = 1; }
103 def : WriteRes<WriteLDHi, []> { let Latency = 4; }
/external/llvm/utils/TableGen/
DSubtargetEmitter.cpp929 Record *WriteRes = in GenSchedClassTables() local
933 if (WriteRes->getValueAsBit("Unsupported")) { in GenSchedClassTables()
937 WLEntry.Cycles += WriteRes->getValueAsInt("Latency"); in GenSchedClassTables()
938 SCDesc.NumMicroOps += WriteRes->getValueAsInt("NumMicroOps"); in GenSchedClassTables()
939 SCDesc.BeginGroup |= WriteRes->getValueAsBit("BeginGroup"); in GenSchedClassTables()
940 SCDesc.EndGroup |= WriteRes->getValueAsBit("EndGroup"); in GenSchedClassTables()
943 RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources"); in GenSchedClassTables()
945 WriteRes->getValueAsListOfInts("ResourceCycles"); in GenSchedClassTables()
/external/llvm/lib/Target/ARM/
DARMScheduleSwift.td130 def : WriteRes<WriteALU, [SwiftUnitP01]>;
144 def : WriteRes<WriteCMP, [SwiftUnitP01]>;
303 def : WriteRes<WriteDiv, [SwiftUnitDiv]>; // Workaround.
532 def : WriteRes<WriteBr, [SwiftUnitP1]> { let Latency = 0; }
533 def : WriteRes<WriteBrL, [SwiftUnitP1]> { let Latency = 2; }
534 def : WriteRes<WriteBrTbl, [SwiftUnitP1, SwiftUnitP2]> { let Latency = 0; }
537 def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; }
611 def : WriteRes<WriteCvtFP, [SwiftUnitP1]> { let Latency = 4; }
1042 def : WriteRes<WritePreLd, [SwiftUnitP2]> { let Latency = 0;
DARMScheduleA9.td1936 def : WriteRes<WriteALUsi, [A9UnitALU]> { let Latency = 2; }
2521 def : WriteRes<WriteDiv, []> { let Latency = 0; }
2523 def : WriteRes<WriteBr, [A9UnitB]>;
2524 def : WriteRes<WriteBrL, [A9UnitB]>;
2525 def : WriteRes<WriteBrTbl, [A9UnitB]>;
2526 def : WriteRes<WritePreLd, []>;
2528 def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; }
DARMSchedule.td48 // def : WriteRes<WriteALUsr, [P01, P01]> {
/external/llvm/lib/Target/AMDGPU/
DSISchedule.td59 int latency> : WriteRes<write, resources> {
/external/llvm/include/llvm/Target/
DTargetSchedule.td27 // each subtarget, define WriteRes and ReadAdvance to associate
128 // specified in WriteRes expire. Setting BufferSize=1 changes this to
230 // Define values common to WriteRes and SchedWriteRes.
280 class WriteRes<SchedWrite write, list<ProcResourceKind> resources>