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/external/vixl/src/vixl/a64/
Dlogic-a64.cc2038 LogicVRegister Simulator::extractnarrow(VectorFormat dstform, in extractnarrow() argument
2048 switch (dstform) { in extractnarrow()
2068 offset = LaneCountFromFormat(dstform) / 2; in extractnarrow()
2071 dst.ClearForWrite(dstform); in extractnarrow()
2076 if (ssrc[i] > MaxIntFromFormat(dstform)) { in extractnarrow()
2078 } else if (ssrc[i] < MinIntFromFormat(dstform)) { in extractnarrow()
2084 if (ssrc[i] > static_cast<int64_t>(MaxUintFromFormat(dstform))) { in extractnarrow()
2090 if (usrc[i] > MaxUintFromFormat(dstform)) { in extractnarrow()
2097 result = ssrc[i] & MaxUintFromFormat(dstform); in extractnarrow()
2099 result = usrc[i] & MaxUintFromFormat(dstform); in extractnarrow()
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