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/external/v8/test/cctest/
Dtest-disasm-mips.cc805 COMPARE(abs_d(f10, f12), "46206285 abs.d f10, f12"); in TEST()
925 COMPARE(sub_s(f10, f8, f6), "46064281 sub.s f10, f8, f6"); in TEST()
926 COMPARE(sub_d(f10, f8, f6), "46264281 sub.d f10, f8, f6"); in TEST()
981 COMPARE(c_s(F, f8, f10, 0), "460a4030 c.f.s f8, f10, cc(0)"); in TEST()
982 COMPARE(c_d(F, f8, f10, 0), "462a4030 c.f.d f8, f10, cc(0)"); in TEST()
984 COMPARE(c_s(UN, f8, f10, 2), "460a4231 c.un.s f8, f10, cc(2)"); in TEST()
985 COMPARE(c_d(UN, f8, f10, 2), "462a4231 c.un.d f8, f10, cc(2)"); in TEST()
987 COMPARE(c_s(EQ, f8, f10, 4), "460a4432 c.eq.s f8, f10, cc(4)"); in TEST()
988 COMPARE(c_d(EQ, f8, f10, 4), "462a4432 c.eq.d f8, f10, cc(4)"); in TEST()
990 COMPARE(c_s(UEQ, f8, f10, 6), "460a4633 c.ueq.s f8, f10, cc(6)"); in TEST()
[all …]
Dtest-disasm-mips64.cc725 COMPARE(abs_d(f10, f12), "46206285 abs.d f10, f12"); in TEST()
862 COMPARE(sub_s(f10, f8, f6), "46064281 sub.s f10, f8, f6"); in TEST()
863 COMPARE(sub_d(f10, f8, f6), "46264281 sub.d f10, f8, f6"); in TEST()
1165 COMPARE(c_s(F, f8, f10, 0), "460a4030 c.f.s f8, f10, cc(0)"); in TEST()
1166 COMPARE(c_d(F, f8, f10, 0), "462a4030 c.f.d f8, f10, cc(0)"); in TEST()
1168 COMPARE(c_s(UN, f8, f10, 2), "460a4231 c.un.s f8, f10, cc(2)"); in TEST()
1169 COMPARE(c_d(UN, f8, f10, 2), "462a4231 c.un.d f8, f10, cc(2)"); in TEST()
1171 COMPARE(c_s(EQ, f8, f10, 4), "460a4432 c.eq.s f8, f10, cc(4)"); in TEST()
1172 COMPARE(c_d(EQ, f8, f10, 4), "462a4432 c.eq.d f8, f10, cc(4)"); in TEST()
1174 COMPARE(c_s(UEQ, f8, f10, 6), "460a4633 c.ueq.s f8, f10, cc(6)"); in TEST()
[all …]
Dtest-assembler-mips.cc287 __ mov_d(f10, f8); // c in TEST()
289 __ sub_d(f10, f10, f12); in TEST()
290 __ sdc1(f10, MemOperand(a0, offsetof(T, d)) ); // d = c - (-b). in TEST()
297 __ mul_d(f10, f10, f14); in TEST()
298 __ sdc1(f10, MemOperand(a0, offsetof(T, e)) ); // e = d * 120 = 1.8066e16. in TEST()
300 __ div_d(f12, f10, f4); in TEST()
320 __ neg_s(f10, f6); // -fb in TEST()
321 __ sub_s(f10, f8, f10); in TEST()
322 __ swc1(f10, MemOperand(a0, offsetof(T, fd)) ); // fd = fc - (-fb). in TEST()
329 __ mul_s(f10, f10, f14); in TEST()
[all …]
/external/webrtc/webrtc/modules/audio_processing/aec/
Daec_rdft_mips.c272 float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14; in cft1st_128_mips() local
511 [f8] "=&f" (f8), [f9] "=&f" (f9), [f10] "=&f" (f10), [f11] "=&f" (f11), in cft1st_128_mips()
521 float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14; in cftmdl_128_mips() local
628 f10 = rdft_w[3]; in cftmdl_128_mips()
713 : [a] "r" (a), [f9] "f" (f9), [f10] "f" (f10), [f11] "f" (f11), in cftmdl_128_mips()
800 : [a] "r" (a), [f9] "f" (f9), [f10] "f" (f10), [f11] "f" (f11), in cftmdl_128_mips()
929 float f1, f2, f3 ,f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15; in rftfsub_128_mips() local
1041 [f9] "=&f" (f9), [f10] "=&f" (f10), [f11] "=&f" (f11), [f12] "=&f" (f12), in rftfsub_128_mips()
1056 float f1, f2, f3 ,f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15; in rftbsub_128_mips() local
1171 [f9] "=&f" (f9), [f10] "=&f" (f10), [f11] "=&f" (f11), [f12] "=&f" (f12), in rftbsub_128_mips()
Daec_core_mips.c345 float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13; in WebRtcAec_FilterFar_mips() local
432 [f9] "=&f" (f9), [f10] "=&f" (f10), [f11] "=&f" (f11), in WebRtcAec_FilterFar_mips()
465 float f0, f1, f2, f3, f4, f5, f6 ,f7, f8, f9, f10, f11, f12; in WebRtcAec_FilterAdaptation_mips() local
530 [f9] "=&f" (f9), [f10] "=&f" (f10), [f11] "=&f" (f11), in WebRtcAec_FilterAdaptation_mips()
/external/llvm/test/CodeGen/SystemZ/
Dframe-04.ll16 ; CHECK: std %f10, 200(%r15)
24 ; CHECK: .cfi_offset %f10, -184
33 ; CHECK: ld %f10, 200(%r15)
76 ; CHECK: std %f10, 184(%r15)
82 ; CHECK: .cfi_offset %f10, -184
91 ; CHECK: ld %f10, 184(%r15)
122 ; numerical order so the pair should be %f8+%f10.
128 ; CHECK: std %f10, 160(%r15)
130 ; CHECK: .cfi_offset %f10, -176
139 ; CHECK: ld %f10, 160(%r15)
[all …]
Dframe-07.ll17 ; CHECK-NOFP: stdy %f10, 4104(%r15)
25 ; CHECK-NOFP: .cfi_offset %f10, -184
34 ; CHECK-NOFP: ldy %f10, 4104(%r15)
51 ; CHECK-FP: stdy %f10, 4104(%r11)
60 ; CHECK-FP: ldy %f10, 4104(%r11)
138 ; CHECK-NOFP: std %f10, 8({{%r[1-5]}},%r15)
146 ; CHECK-NOFP: .cfi_offset %f10, -184
155 ; CHECK-NOFP: ld %f10, 8({{%r[1-5]}},%r15)
171 ; CHECK-FP: std %f10, 8({{%r[1-5]}},%r11)
179 ; CHECK-FP: .cfi_offset %f10, -184
[all …]
Dframe-03.ll17 ; CHECK: std %f10, 200(%r15)
25 ; CHECK: .cfi_offset %f10, -184
34 ; CHECK: ld %f10, 200(%r15)
101 ; CHECK: std %f10, 192(%r15)
108 ; CHECK: .cfi_offset %f10, -184
117 ; CHECK: ld %f10, 192(%r15)
180 ; CHECK-NOT: %f10
227 ; CHECK-NOT: %f10
Dframe-02.ll15 ; CHECK: std %f10, 200(%r15)
23 ; CHECK: .cfi_offset %f10, -184
32 ; CHECK: ld %f10, 200(%r15)
99 ; CHECK: std %f10, 192(%r15)
106 ; CHECK: .cfi_offset %f10, -184
115 ; CHECK: ld %f10, 192(%r15)
178 ; CHECK-NOT: %f10
225 ; CHECK-NOT: %f10
Dframe-17.ll13 ; CHECK: std %f10, 208(%r15)
26 ; CHECK: ld %f10, 208(%r15)
77 ; CHECK: std %f10, 208(%r15)
87 ; CHECK: ld %f10, 208(%r15)
138 ; CHECK: std %f10, 216(%r15)
150 ; CHECK: ld %f10, 216(%r15)
/external/mesa3d/src/mesa/sparc/
Dnorm.S67 fmuls %f2, M2, %f10 ! FGM Group f5 available
72 fadds %f3, %f10, %f3 ! FGA Group f10 available
81 fmuls %f7, %f7, %f10 ! FGM Group f7 available
83 fadds %f6, %f10, %f6 ! FGA Group 4cyc stall f6,f10 available
132 fmuls %f2, M2, %f10 ! FGM Group f5 available
137 fadds %f3, %f10, %f3 ! FGA Group f10 available
208 fmuls %f7, %f7, %f10 ! FGM Group f7 available
210 fadds %f6, %f10, %f6 ! FGA Group 4cyc stall f6,f10 available
365 fmuls %f2, M2, %f10 ! FGM Group f5 available
370 fadds %f3, %f10, %f3 ! FGA Group f10 available
[all …]
Dxform.S89 fmuls %f8, M1, %f10 ! FGM Group f2 available
100 fadds %f10, M13, %f10 ! FGA Group f10 available
101 st %f10, [%g2 + 0x14] ! LSU
200 fmuls %f8, M1, %f10 ! FGM Group
207 fadds %f10, M13, %f12 ! FGA Group f10 available
545 fmuls %f8, M0, %f10 ! FGM Group f2 available
551 fadds %f10, M12, %f10 ! FGA Group f2, f10 available
557 fadds %f10, %f12, %f10 ! FGA Group f10 available
558 st %f10, [%g2 + 0x10] ! LSU
667 ld [%g1 + 0x04], %f10 ! LSU Group
[all …]
/external/llvm/test/MC/SystemZ/
Dregs-good.s62 #CHECK: ler %f10, %f11 # encoding: [0x38,0xab]
71 ler %f10,%f11
80 #CHECK: ldr %f10, %f11 # encoding: [0x28,0xab]
89 ldr %f10,%f11
129 #CHECK: .cfi_offset %f10, 208
163 .cfi_offset %f10,208
/external/v8/test/webkit/
DtoString-elision-trailing-comma-expected.txt75 PASS f10().length is 5
76 PASS f10()[5-1] is undefined
77 PASS unevalf(eval(unevalf(f10))) is unevalf(f10)
78 PASS eval(unevalf(f10))().length is 5
79 PASS eval(unevalf(f10))()[5-1] is undefined
/external/clang/test/Sema/
Dwarn-unused-function.c37 static void f10(void); // expected-warning{{unused}}
38 static void f10(void);
/external/v8/test/mjsunit/compiler/
Dloopcount.js89 function f10(x) { function
92 f10(42);
/external/clang/test/CodeGenCXX/
Dmangle-variadic-templates.cpp74 template<typename ...T> void f10(ArrayOfN<T...> &) {} in f10() function
77 template void f10<int, float>(int (&)[2]);
/external/clang/test/CXX/except/except.spec/
Dp5-virtual.cpp38 virtual void f10() noexcept(false);
74 virtual void f10() noexcept(false);
/external/llvm/test/MC/Mips/
Dmips-reginfo-fp32.s29 # ceil.w.s - Reads $f8 and writes to $f10.
30 ceil.w.s $f10, $f8
/external/llvm/test/CodeGen/ARM/
Dfpconv.ll94 define double @f10(i32 %a) {
95 ;CHECK-VFP-LABEL: f10:
97 ;CHECK-LABEL: f10:
/external/llvm/test/Analysis/LazyCallGraph/
Dbasic.ll41 define void @f10() {
70 ; CHECK-NEXT: -> f10
94 invoke void @f10() to label %exit unwind label %unwind
161 ; CHECK-NEXT: f10
/external/llvm/test/CodeGen/PowerPC/
Dppc64-fastcc.ll5 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
13 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
21 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
29 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
37 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
45 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
53 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
61 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
69 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
77 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
[all …]
/external/valgrind/none/tests/mips32/
DMoveIns.c293 TESTINSNMOVE("mfc1 $s1, $f10", 40, f10, s1); in main()
322 TESTINSNMOVEt("mtc1 $s1, $f10", 40, f10, s1); in main()
351 TESTINSNMOVE1s("mov.s $f9, $f10", 40, f9, f10); in main()
352 TESTINSNMOVE1s("mov.s $f10, $f11", 44, f10, f11); in main()
379 TESTINSNMOVE1d("mov.d $f8, $f10", 0, f8, f10); in main()
380 TESTINSNMOVE1d("mov.d $f8, $f10", 8, f8, f10); in main()
381 TESTINSNMOVE1d("mov.d $f10, $f12", 16, f10, f12); in main()
382 TESTINSNMOVE1d("mov.d $f10, $f12", 24, f10, f12); in main()
/external/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-xfail-mips64r2.txt28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
33 0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10
54 0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6
58 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
61 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
/external/llvm/test/MC/Disassembler/Mips/mips64r5/
Dvalid-xfail-mips64r5.txt28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
33 0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10
54 0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6
58 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
61 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20

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