| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | select.ll | 207 ; M2: mov.s $f12, $f14
208 ; M3: mov.s $f12, $f13
211 ; M2-M3: mov.s $f0, $f12
214 ; CMOV-32: movn.s $f14, $f12, $[[T0]]
218 ; SEL-32: sel.s $f0, $f14, $f12
221 ; CMOV-64: movn.s $f13, $f12, $[[T0]]
225 ; SEL-64: sel.s $f0, $f13, $f12
285 ; M2: mov.d $f12, $f14
288 ; M2: mov.d $f0, $f12
292 ; CMOV-32: movn.d $f14, $f12, $[[T1]]
[all …]
|
| /external/llvm/test/MC/Mips/ |
| D | mips-fpu-instructions.s | 9 # CHECK: abs.d $f12, $f14 # encoding: [0x05,0x73,0x20,0x46]
11 # CHECK: add.d $f8, $f12, $f14 # encoding: [0x00,0x62,0x2e,0x46]
13 # CHECK: floor.w.d $f12, $f14 # encoding: [0x0f,0x73,0x20,0x46]
15 # CHECK: ceil.w.d $f12, $f14 # encoding: [0x0e,0x73,0x20,0x46]
17 # CHECK: mul.d $f8, $f12, $f14 # encoding: [0x02,0x62,0x2e,0x46]
19 # CHECK: neg.d $f12, $f14 # encoding: [0x07,0x73,0x20,0x46]
21 # CHECK: round.w.d $f12, $f14 # encoding: [0x0c,0x73,0x20,0x46]
23 # CHECK: sqrt.d $f12, $f14 # encoding: [0x04,0x73,0x20,0x46]
25 # CHECK: sub.d $f8, $f12, $f14 # encoding: [0x01,0x62,0x2e,0x46]
27 # CHECK: trunc.w.d $f12, $f14 # encoding: [0x0d,0x73,0x20,0x46]
[all …]
|
| /external/llvm/test/CodeGen/Mips/ |
| D | fcmp.ll | 29 ; 32-C-DAG: c.eq.s $f12, $f14
33 ; 64-C-DAG: c.eq.s $f12, $f13
36 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
40 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
53 ; 32-C-DAG: c.ule.s $f12, $f14
57 ; 64-C-DAG: c.ule.s $f12, $f13
60 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
64 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
77 ; 32-C-DAG: c.ult.s $f12, $f14
81 ; 64-C-DAG: c.ult.s $f12, $f13
[all …]
|
| D | fmadd1.ll | 26 ; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
32 ; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
37 ; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
42 ; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
46 ; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
50 ; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
66 ; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
72 ; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
77 ; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
82 ; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
[all …]
|
| D | o32_cc.ll | 7 ; $f12, $f14
9 ; ALL-DAG: ldc1 $f12, %lo
19 ; $f12, $f14
21 ; ALL-DAG: lwc1 $f12, %lo
31 ; $f12, $f14
33 ; ALL-DAG: lwc1 $f12, %lo
43 ; $f12, $f14
45 ; ALL-DAG: ldc1 $f12, %lo
69 ; $f12, $6, stack
71 ; ALL-DAG: ldc1 $f12, %lo
[all …]
|
| D | fpbr.ll | 12 ; 32-FCC: c.eq.s $f12, $f14
13 ; 64-FCC: c.eq.s $f12, $f13
16 ; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14
17 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
46 ; 32-FCC: c.olt.s $f12, $f14
47 ; 64-FCC: c.olt.s $f12, $f13
50 ; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12
51 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
75 ; 32-FCC: c.ole.s $f12, $f14
76 ; 64-FCC: c.ole.s $f12, $f13
[all …]
|
| D | no-odd-spreg.ll | 15 ; Clobber all except $f12 and $f13
18 ; allocator will choose $f12 and $f13 to avoid the spill/reload.
30 ; ODDSPREG: add.s $f13, $f12, ${{f[0-9]+}}
33 ; ODDSPREG: add.s $f0, $f12, $f13
35 ; NOODDSPREG: add.s $[[T0:f[0-9]*[02468]]], $f12, ${{f[0-9]+}}
38 ; NOODDSPREG: add.s $f0, $f12, $[[T1]]
42 ; Clobber all except $f12 and $f13
45 ; use $f12 and $f13.
54 ; ALL: add.d $[[T0:f[0-9]+]], $f12, ${{f[0-9]+}}
55 ; ALL: add.d $f0, $f12, $[[T0]]
|
| D | mno-ldc1-sdc1.ll | 120 ; 32R1-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
125 ; 32R2-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
126 ; 32R2-LE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
130 ; 32R6-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
131 ; 32R6-LE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
135 ; 32R1-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
142 ; 32R2-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
143 ; 32R2-LE-STATIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
149 ; 32R6-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
150 ; 32R6-LE-STATIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
[all …]
|
| D | select.ll | 207 ; 32: movt.s $f14, $f12, $fcc0
213 ; 32R2: movt.s $f14, $f12, $fcc0
219 ; 32R6: sel.s $[[CC]], $f14, $f12
222 ; 64: movt.s $f13, $f12, $fcc0
226 ; 64R2: movt.s $f13, $f12, $fcc0
230 ; 64R6: sel.s $[[CC]], $f13, $f12
244 ; 32: movt.s $f14, $f12, $fcc0
250 ; 32R2: movt.s $f14, $f12, $fcc0
256 ; 32R6: sel.s $[[CC]], $f14, $f12
259 ; 64: movt.s $f13, $f12, $fcc0
[all …]
|
| D | no-odd-spreg-msa.ll | 14 %b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)
17 ; Clobber all except $f12/$w12 and $f13
20 ; allocator will choose $f12/$w12 for the vector and $f13 for the float to
33 ; ALL: mov.s $f13, $f12
48 %b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)
51 ; Clobber all except $f12/$w12 and $f13
54 ; allocator will choose $f12/$w12 for the vector and $f13 for the float to
67 ; ALL: mov.s $f13, $f12
83 ; Clobber all except $f12, and $f13
89 ; must move it to $f12/$w12.
[all …]
|
| /external/llvm/test/CodeGen/X86/ |
| D | field-extract-use-trunc.ll | 4 define i32 @test(i32 %f12) nounwind {
5 %tmp7.25 = lshr i32 %f12, 16
11 define i32 @test2(i32 %f12) nounwind {
12 %f11 = shl i32 %f12, 8
17 define i32 @test3(i32 %f12) nounwind {
18 %f11 = shl i32 %f12, 13
23 define i64 @test4(i64 %f12) nounwind {
24 %f11 = shl i64 %f12, 32
29 define i16 @test5(i16 %f12) nounwind {
30 %f11 = shl i16 %f12, 2
[all …]
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| D | valid-mips32r3-el.txt | 2 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
5 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
23 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
25 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
27 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
29 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
31 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
33 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
35 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
37 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]
|
| D | valid-mips32r3.txt | 236 0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14
237 0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
238 0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14
239 0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14
240 0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14
241 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14
242 0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14
243 0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14
244 0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14
245 0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14
[all …]
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| D | valid-mips32r5-el.txt | 2 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
5 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
23 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
25 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
27 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
29 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
31 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
33 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
35 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
37 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]
|
| D | valid-mips32r5.txt | 237 0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14
238 0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
239 0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14
240 0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14
241 0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14
242 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14
243 0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14
244 0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14
245 0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14
246 0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14
[all …]
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| D | valid-mips32r2-el.txt | 5 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
8 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
26 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
28 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
30 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
32 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
34 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
36 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
38 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
40 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]
|
| D | valid-mips32r2.txt | 239 0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14
240 0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
241 0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14
242 0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14
243 0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14
244 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14
245 0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14
246 0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14
247 0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14
248 0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14
[all …]
|
| /external/llvm/test/MC/Disassembler/Mips/mips32/ |
| D | valid-mips32-el.txt | 2 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
5 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
25 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
27 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
29 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
31 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
33 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
35 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
37 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
39 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]
|
| D | valid-mips32.txt | 226 0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14
227 0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
228 0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14
229 0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14
230 0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14
231 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14
232 0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14
233 0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14
234 0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14
243 0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14
[all …]
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| D | valid-mips64r5-el.txt | 3 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
6 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
24 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
26 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
28 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
30 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
32 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
34 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
36 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
38 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| D | valid-mips64r3-el.txt | 3 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
6 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
24 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
26 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
28 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
30 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
32 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
34 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
36 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
38 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| D | valid-mips64-el.txt | 2 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
5 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
23 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
25 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
27 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
29 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
31 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
33 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
35 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
37 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]
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| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| D | valid-mips64r2-el.txt | 6 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
9 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
27 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
29 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
31 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
33 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
35 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
37 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
39 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
41 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]
|
| /external/webrtc/webrtc/modules/audio_processing/aec/ |
| D | aec_rdft_mips.c | 272 float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14; in cft1st_128_mips() local
512 [f12] "=&f" (f12), [f13] "=&f" (f13), [f14] "=&f" (f14), in cft1st_128_mips()
521 float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14; in cftmdl_128_mips() local
630 f12 = rdft_w[5]; in cftmdl_128_mips()
714 [f12] "f" (f12), [f13] "f" (f13), [f14] "f" (f14) in cftmdl_128_mips()
718 f12 = rdft_w[7]; in cftmdl_128_mips()
801 [f12] "f" (f12), [f13] "f" (f13), [f14] "f" (f14) in cftmdl_128_mips()
929 float f1, f2, f3 ,f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15; in rftfsub_128_mips() local
1041 [f9] "=&f" (f9), [f10] "=&f" (f10), [f11] "=&f" (f11), [f12] "=&f" (f12), in rftfsub_128_mips()
1056 float f1, f2, f3 ,f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15; in rftbsub_128_mips() local
[all …]
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| /external/v8/test/mjsunit/harmony/ |
| D | default-parameters.js | 126 var f12 = function f(x = f) { function f() {}; return x; } function in TestParameterScopingSloppy
127 assertSame(f12, f12());
164 var f12 = function f(x = f) { const f = 0; return x; } function in TestParameterScopingStrict
165 assertSame(f12, f12());
187 function f12(z = eval("var y = 2"), b = y) {} function in TestSloppyEvalScoping
188 assertThrows(f12, ReferenceError);
245 function f12(z = eval("var y = 2"), b = y) {} function in TestStrictEvalScoping
246 assertThrows(f12, ReferenceError);
280 function f12(a = eval("x"), x = 2) { return a } function in TestParameterTDZSloppy
281 assertThrows(() => f12(), ReferenceError);
[all …]
|