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/external/llvm/test/MC/ARM/
Dfullfp16-neon.s4 vadd.f16 d0, d1, d2
5 vadd.f16 q0, q1, q2
6 @ ARM: vadd.f16 d0, d1, d2 @ encoding: [0x02,0x0d,0x11,0xf2]
7 @ ARM: vadd.f16 q0, q1, q2 @ encoding: [0x44,0x0d,0x12,0xf2]
8 @ THUMB: vadd.f16 d0, d1, d2 @ encoding: [0x11,0xef,0x02,0x0d]
9 @ THUMB: vadd.f16 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x0d]
11 vsub.f16 d0, d1, d2
12 vsub.f16 q0, q1, q2
13 @ ARM: vsub.f16 d0, d1, d2 @ encoding: [0x02,0x0d,0x31,0xf2]
14 @ ARM: vsub.f16 q0, q1, q2 @ encoding: [0x44,0x0d,0x32,0xf2]
[all …]
Dfullfp16-neon-neg.s6 vadd.f16 d0, d1, d2
7 vadd.f16 q0, q1, q2
11 vsub.f16 d0, d1, d2
12 vsub.f16 q0, q1, q2
16 vmul.f16 d0, d1, d2
17 vmul.f16 q0, q1, q2
21 vmul.f16 d1, d2, d3[2]
22 vmul.f16 q4, q5, d6[3]
26 vmla.f16 d0, d1, d2
27 vmla.f16 q0, q1, q2
[all …]
Dneon-vcvt-fp16.s6 @ CHECK-FP16: vcvtt.f32.f16 s7, s1 @ encoding: [0xe0,0x3a,0xf2,0xee]
8 vcvtt.f32.f16 s7, s1
9 @ CHECK-FP16: vcvtt.f16.f32 s1, s7 @ encoding: [0xe3,0x0a,0xf3,0xee]
11 vcvtt.f16.f32 s1, s7
13 @ CHECK-FP16: vcvtb.f32.f16 s7, s1 @ encoding: [0x60,0x3a,0xf2,0xee]
15 vcvtb.f32.f16 s7, s1
16 @ CHECK-FP16: vcvtb.f16.f32 s1, s7 @ encoding: [0x63,0x0a,0xf3,0xee]
18 vcvtb.f16.f32 s1, s7
Dthumb-fp-armv8.s5 vcvtt.f64.f16 d3, s1
6 @ CHECK: vcvtt.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0xe0,0x3b]
7 vcvtt.f16.f64 s5, d12
8 @ CHECK: vcvtt.f16.f64 s5, d12 @ encoding: [0xf3,0xee,0xcc,0x2b]
10 vcvtb.f64.f16 d3, s1
11 @ CHECK: vcvtb.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0x60,0x3b]
12 vcvtb.f16.f64 s4, d1
13 @ CHECK: vcvtb.f16.f64 s4, d1 @ encoding: [0xb3,0xee,0x41,0x2b]
16 vcvttge.f64.f16 d3, s1
17 @ CHECK: vcvttge.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0xe0,0x3b]
[all …]
Dfp-armv8.s5 vcvtt.f64.f16 d3, s1
6 @ CHECK: vcvtt.f64.f16 d3, s1 @ encoding: [0xe0,0x3b,0xb2,0xee]
7 vcvtt.f16.f64 s5, d12
8 @ CHECK: vcvtt.f16.f64 s5, d12 @ encoding: [0xcc,0x2b,0xf3,0xee]
10 vcvtb.f64.f16 d3, s1
11 @ CHECK: vcvtb.f64.f16 d3, s1 @ encoding: [0x60,0x3b,0xb2,0xee]
12 vcvtb.f16.f64 s4, d1
13 @ CHECK: vcvtb.f16.f64 s4, d1 @ encoding: [0x41,0x2b,0xb3,0xee]
15 vcvttge.f64.f16 d3, s1
16 @ CHECK: vcvttge.f64.f16 d3, s1 @ encoding: [0xe0,0x3b,0xb2,0xae]
[all …]
Dinvalid-fp-armv8.s5 vcvtt.f64.f16 d3, s1
6 @ V7-NOT: vcvtt.f64.f16 d3, s1 @ encoding: [0xe0,0x3b,0xb2,0xee]
7 vcvtt.f16.f64 s5, d12
8 @ V7-NOT: vcvtt.f16.f64 s5, d12 @ encoding: [0xcc,0x2b,0xf3,0xee]
68 vcvtbgt.f64.f16 q0, d3
70 vcvttlt.f64.f16 s0, s3
72 vcvttvs.f16.f64 s0, s3
74 vcvtthi.f16.f64 q0, d3
/external/llvm/test/MC/Disassembler/ARM/
Dfullfp16-neon-thumb.txt4 # CHECK: vadd.f16 d0, d1, d2
5 # CHECK: vadd.f16 q0, q1, q2
9 # CHECK: vsub.f16 d0, d1, d2
10 # CHECK: vsub.f16 q0, q1, q2
14 # CHECK: vmul.f16 d0, d1, d2
15 # CHECK: vmul.f16 q0, q1, q2
19 # CHECK: vmul.f16 d1, d2, d3[2]
20 # CHECK: vmul.f16 q4, q5, d6[3]
24 # CHECK: vmla.f16 d0, d1, d2
25 # CHECK: vmla.f16 q0, q1, q2
[all …]
Dfullfp16-neon-arm.txt4 # CHECK: vadd.f16 d0, d1, d2
5 # CHECK: vadd.f16 q0, q1, q2
9 # CHECK: vsub.f16 d0, d1, d2
10 # CHECK: vsub.f16 q0, q1, q2
14 # CHECK: vmul.f16 d0, d1, d2
15 # CHECK: vmul.f16 q0, q1, q2
19 # CHECK: vmul.f16 d1, d2, d3[2]
20 # CHECK: vmul.f16 q4, q5, d6[3]
24 # CHECK: vmla.f16 d0, d1, d2
25 # CHECK: vmla.f16 q0, q1, q2
[all …]
Dfp-armv8.txt4 # CHECK: vcvtt.f64.f16 d3, s1
7 # CHECK: vcvtt.f16.f64 s5, d12
10 # CHECK: vcvtb.f64.f16 d3, s1
13 # CHECK: vcvtb.f16.f64 s4, d1
16 # CHECK: vcvttge.f64.f16 d3, s1
19 # CHECK: vcvttgt.f16.f64 s5, d12
22 # CHECK: vcvtbeq.f64.f16 d3, s1
25 # CHECK: vcvtblt.f16.f64 s4, d1
Dthumb-fp-armv8.txt4 # CHECK: vcvtt.f64.f16 d3, s1
7 # CHECK: vcvtt.f16.f64 s5, d12
10 # CHECK: vcvtb.f64.f16 d3, s1
13 # CHECK: vcvtb.f16.f64 s4, d1
17 # CHECK: vcvttge.f64.f16 d3, s1
21 # CHECK: vcvttgt.f16.f64 s5, d12
25 # CHECK: vcvtbeq.f64.f16 d3, s1
29 # CHECK: vcvtblt.f16.f64 s4, d1
/external/valgrind/none/tests/ppc64/
Dtest_dfp3.c32 register double f16 __asm__ ("fr16");
91 __asm__ __volatile__ ("drintx 1, %0, %1, 0" : "=f" (f18) : "f" (f16)); in _test_drintx()
93 __asm__ __volatile__ ("drintx 0, %0, %1, 0" : "=f" (f18) : "f" (f16)); in _test_drintx()
97 __asm__ __volatile__ ("drintx 1, %0, %1, 1" : "=f" (f18) : "f" (f16)); in _test_drintx()
99 __asm__ __volatile__ ("drintx 0, %0, %1, 1" : "=f" (f18) : "f" (f16)); in _test_drintx()
103 __asm__ __volatile__ ("drintx 1, %0, %1, 2" : "=f" (f18) : "f" (f16)); in _test_drintx()
105 __asm__ __volatile__ ("drintx 0, %0, %1, 2" : "=f" (f18) : "f" (f16)); in _test_drintx()
109 __asm__ __volatile__ ("drintx 1, %0, %1, 3" : "=f" (f18) : "f" (f16)); in _test_drintx()
111 __asm__ __volatile__ ("drintx 0, %0, %1, 3" : "=f" (f18) : "f" (f16)); in _test_drintx()
127 __asm__ __volatile__ ("drintn 1, %0, %1, 0" : "=f" (f18) : "f" (f16)); in _test_drintn()
[all …]
Dtest_dfp5.c98 _Decimal64 f16 = valB->dec_val; in _test_dtstsf() local
106 __asm__ __volatile__ ("dtstsf %0, %1, %2" : : "i" (BF_val1), "f" (f14), "f" (f16)); in _test_dtstsf()
109 __asm__ __volatile__ ("dtstsf %0, %1, %2" : : "i" (BF_val2), "f" (f14), "f" (f16)); in _test_dtstsf()
112 __asm__ __volatile__ ("dtstsf %0, %1, %2" : : "i" (BF_val3), "f" (f14), "f" (f16)); in _test_dtstsf()
122 _Decimal128 f16 = valB->dec_val128; in _test_dtstsfq() local
130 __asm__ __volatile__ ("dtstsfq %0, %1, %2" : : "i" (BF_val1), "f" (f14), "f" (f16)); in _test_dtstsfq()
133 __asm__ __volatile__ ("dtstsfq %0, %1, %2" : : "i" (BF_val2), "f" (f14), "f" (f16)); in _test_dtstsfq()
136 __asm__ __volatile__ ("dtstsfq %0, %1, %2" : : "i" (BF_val3), "f" (f14), "f" (f16)); in _test_dtstsfq()
148 _Decimal64 f16 = valB->dec_val; in _test_ddedpd() local
151 __asm__ __volatile__ ("ddedpd. 0, %0, %1" : "=f" (ret) : "f" (f16)); in _test_ddedpd()
[all …]
Dtest_dfp1.c31 register double f16 __asm__ ("fr16");
85 __asm__ __volatile__ ("dadd. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dadd()
87 __asm__ __volatile__ ("dadd %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dadd()
93 __asm__ __volatile__ ("dsub. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dsub()
95 __asm__ __volatile__ ("dsub %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dsub()
101 __asm__ __volatile__ ("dmul. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dmul()
103 __asm__ __volatile__ ("dmul %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dmul()
109 __asm__ __volatile__ ("ddiv. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_ddiv()
111 __asm__ __volatile__ ("ddiv %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_ddiv()
118 __asm__ __volatile__ ("daddq. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_daddq()
[all …]
/external/valgrind/none/tests/ppc32/
Dtest_dfp3.c32 register double f16 __asm__ ("fr16");
91 __asm__ __volatile__ ("drintx 1, %0, %1, 0" : "=f" (f18) : "f" (f16)); in _test_drintx()
93 __asm__ __volatile__ ("drintx 0, %0, %1, 0" : "=f" (f18) : "f" (f16)); in _test_drintx()
97 __asm__ __volatile__ ("drintx 1, %0, %1, 1" : "=f" (f18) : "f" (f16)); in _test_drintx()
99 __asm__ __volatile__ ("drintx 0, %0, %1, 1" : "=f" (f18) : "f" (f16)); in _test_drintx()
103 __asm__ __volatile__ ("drintx 1, %0, %1, 2" : "=f" (f18) : "f" (f16)); in _test_drintx()
105 __asm__ __volatile__ ("drintx 0, %0, %1, 2" : "=f" (f18) : "f" (f16)); in _test_drintx()
109 __asm__ __volatile__ ("drintx 1, %0, %1, 3" : "=f" (f18) : "f" (f16)); in _test_drintx()
111 __asm__ __volatile__ ("drintx 0, %0, %1, 3" : "=f" (f18) : "f" (f16)); in _test_drintx()
127 __asm__ __volatile__ ("drintn 1, %0, %1, 0" : "=f" (f18) : "f" (f16)); in _test_drintn()
[all …]
Dtest_dfp5.c98 _Decimal64 f16 = valB->dec_val; in _test_dtstsf() local
106 __asm__ __volatile__ ("dtstsf %0, %1, %2" : : "i" (BF_val1), "f" (f14), "f" (f16)); in _test_dtstsf()
109 __asm__ __volatile__ ("dtstsf %0, %1, %2" : : "i" (BF_val2), "f" (f14), "f" (f16)); in _test_dtstsf()
112 __asm__ __volatile__ ("dtstsf %0, %1, %2" : : "i" (BF_val3), "f" (f14), "f" (f16)); in _test_dtstsf()
122 _Decimal128 f16 = valB->dec_val128; in _test_dtstsfq() local
130 __asm__ __volatile__ ("dtstsfq %0, %1, %2" : : "i" (BF_val1), "f" (f14), "f" (f16)); in _test_dtstsfq()
133 __asm__ __volatile__ ("dtstsfq %0, %1, %2" : : "i" (BF_val2), "f" (f14), "f" (f16)); in _test_dtstsfq()
136 __asm__ __volatile__ ("dtstsfq %0, %1, %2" : : "i" (BF_val3), "f" (f14), "f" (f16)); in _test_dtstsfq()
148 _Decimal64 f16 = valB->dec_val; in _test_ddedpd() local
151 __asm__ __volatile__ ("ddedpd. 0, %0, %1" : "=f" (ret) : "f" (f16)); in _test_ddedpd()
[all …]
Dtest_dfp1.c31 register double f16 __asm__ ("fr16");
85 __asm__ __volatile__ ("dadd. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dadd()
87 __asm__ __volatile__ ("dadd %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dadd()
93 __asm__ __volatile__ ("dsub. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dsub()
95 __asm__ __volatile__ ("dsub %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dsub()
101 __asm__ __volatile__ ("dmul. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dmul()
103 __asm__ __volatile__ ("dmul %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dmul()
109 __asm__ __volatile__ ("ddiv. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_ddiv()
111 __asm__ __volatile__ ("ddiv %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_ddiv()
118 __asm__ __volatile__ ("daddq. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_daddq()
[all …]
/external/llvm/test/CodeGen/ARM/
Dfp16-promote.ll9 ; CHECK-FP16: vcvtb.f32.f16
10 ; CHECK-FP16: vcvtb.f32.f16
15 ; CHECK-FP16: vcvtb.f16.f32
26 ; CHECK-FP16: vcvtb.f32.f16
27 ; CHECK-FP16: vcvtb.f32.f16
32 ; CHECK-FP16: vcvtb.f16.f32
43 ; CHECK-FP16: vcvtb.f32.f16
44 ; CHECK-FP16: vcvtb.f32.f16
49 ; CHECK-FP16: vcvtb.f16.f32
60 ; CHECK-FP16: vcvtb.f32.f16
[all …]
Dfp16-args.ll24 ; SOFT: vcvtb.f32.f16 {{s[0-9]+}}, {{s[0-9]+}}
25 ; SOFT: vcvtb.f32.f16 {{s[0-9]+}}, {{s[0-9]+}}
27 ; SOFT: vcvtb.f16.f32 {{s[0-9]+}}, {{s[0-9]+}}
32 ; HARD: vcvtb.f32.f16 {{s[0-9]+}}, s1
33 ; HARD: vcvtb.f32.f16 {{s[0-9]+}}, s0
35 ; HARD: vcvtb.f16.f32 [[SREG:s[0-9]+]], {{s[0-9]+}}
Dhalf.ll34 ; CHECK-F16: vcvtb.f32.f16
35 ; CHECK-V8: vcvtb.f32.f16
46 ; CHECK-F16: vcvtb.f32.f16
48 ; CHECK-V8: vcvtb.f64.f16
58 ; CHECK-F16: vcvtb.f16.f32
59 ; CHECK-V8: vcvtb.f16.f32
70 ; CHECK-V8: vcvtb.f16.f64
Dfp16.ll23 ; CHECK-FP16: vcvtb.f32.f16
24 ; CHECK-ARMv8: vcvtb.f32.f16
30 ; CHECK-FP16: vcvtb.f32.f16
31 ; CHECK-ARMV8: vcvtb.f32.f16
38 ; CHECK-FP16: vcvtb.f16.f32
39 ; CHECK-ARMV8: vcvtb.f16.f32
58 ; CHECK-FP16: vcvtb.f32.f16 [[TMP32:s[0-9]+]], [[TMP16]]
62 ; CHECK-ARMV8: vcvtb.f64.f16 d0, [[TMP]]
81 ; CHECK-ARMV8: vcvtb.f16.f64 [[TMP:s[0-9]+]], d0
Dfp16-v3.ll7 ; CHECK: vcvtb.f32.f16
10 ; CHECK-NEXT: vcvtb.f16.f32 [[SREG:s[0-9]+]], {{.*}}
29 ; CHECK: vcvtb.f16.f32
30 ; CHECK: vcvtb.f16.f32
31 ; CHECK: vcvtb.f16.f32
/external/mesa3d/src/gallium/auxiliary/util/
Du_half.h56 uint16_t f16; in util_float_to_half() local
68 f16 = 0x7c00; in util_float_to_half()
71 f16 = 0x7e00; in util_float_to_half()
82 f16 = f32.ui >> 13; in util_float_to_half()
86 f16 |= sign >> 16; in util_float_to_half()
88 return f16; in util_float_to_half()
92 util_half_to_float(uint16_t f16) in util_half_to_float() argument
103 f32.ui = (f16 & 0x7fff) << 13; in util_half_to_float()
113 f32.ui |= (f16 & 0x8000) << 16; in util_half_to_float()
/external/clang/test/CodeGen/
Dtbaa.cpp11 uint16_t f16; member
18 uint16_t f16; member
24 uint16_t f16; member
30 uint16_t f16; member
38 uint16_t f16; member
43 uint16_t f16; member
67 A->f16 = 4; in g2()
91 B->a.f16 = 4; in g4()
139 S->f16 = 4; in g8()
163 S2->f16 = 4; in g10()
Dtbaa-class.cpp12 uint16_t f16; member in StructA
20 uint16_t f16; member in StructB
27 uint16_t f16; member in StructC
34 uint16_t f16; member in StructD
43 uint16_t f16; member in StructS
73 A->f16 = 4; in g2()
97 B->a.f16 = 4; in g4()
145 S->f16 = 4; in g8()
/external/llvm/test/CodeGen/AArch64/
Df16-instructions.ll500 declare half @llvm.sqrt.f16(half %a) #0
501 declare half @llvm.powi.f16(half %a, i32 %b) #0
502 declare half @llvm.sin.f16(half %a) #0
503 declare half @llvm.cos.f16(half %a) #0
504 declare half @llvm.pow.f16(half %a, half %b) #0
505 declare half @llvm.exp.f16(half %a) #0
506 declare half @llvm.exp2.f16(half %a) #0
507 declare half @llvm.log.f16(half %a) #0
508 declare half @llvm.log10.f16(half %a) #0
509 declare half @llvm.log2.f16(half %a) #0
[all …]

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