/external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
D | valid-xfail-mips64r2.txt | 18 0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 20 0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 35 0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20 39 0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20 41 0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8 51 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20 56 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2 61 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
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/external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
D | valid-xfail-mips64r5.txt | 18 0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 20 0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 35 0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20 39 0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20 41 0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8 51 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20 56 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2 61 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
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/external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
D | valid-xfail-mips64r3.txt | 18 0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 20 0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 35 0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20 39 0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20 41 0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8 51 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20 56 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2 61 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
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/external/llvm/test/MC/Mips/mips1/ |
D | valid.s | 37 cvt.w.d $f20,$f14 38 cvt.w.s $f20,$f24 40 div.d $f29,$f20,$f27 65 mov.d $f20,$f14 73 mul.d $f20,$f20,$f16
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/external/llvm/test/MC/Mips/mips2/ |
D | valid.s | 44 ceil.w.s $f6,$f20 51 cvt.w.d $f20,$f14 52 cvt.w.s $f20,$f24 54 div.d $f29,$f20,$f27 85 mov.d $f20,$f14 93 mul.d $f20,$f20,$f16
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/external/llvm/test/MC/Mips/mips5/ |
D | valid.s | 51 ceil.w.s $f6,$f20 62 cvt.w.d $f20,$f14 63 cvt.w.s $f20,$f24 77 div.d $f29,$f20,$f27 146 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1] 152 mov.d $f20,$f14 176 mul.d $f20,$f20,$f16 186 nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1] 189 nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38]
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/external/llvm/test/MC/Mips/mips64/ |
D | valid.s | 51 ceil.w.s $f6,$f20 64 cvt.w.d $f20,$f14 65 cvt.w.s $f20,$f24 82 div.d $f29,$f20,$f27 157 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1] 164 mov.d $f20,$f14 192 mul.d $f20,$f20,$f16 202 nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1] 205 nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38]
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/external/llvm/test/MC/Mips/mips4/ |
D | valid.s | 51 ceil.w.s $f6,$f20 62 cvt.w.d $f20,$f14 63 cvt.w.s $f20,$f24 77 div.d $f29,$f20,$f27 145 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1] 151 mov.d $f20,$f14 175 mul.d $f20,$f20,$f16 185 nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1] 188 nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38]
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/external/llvm/test/MC/Mips/mips32/ |
D | valid.s | 49 ceil.w.s $f6,$f20 58 cvt.w.d $f20,$f14 59 cvt.w.s $f20,$f24 62 div.d $f29,$f20,$f27 97 mov.d $f20,$f14 121 mul.d $f20,$f20,$f16
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/external/llvm/test/MC/Mips/mips32r3/ |
D | valid.s | 49 ceil.w.s $f6,$f20 60 cvt.w.d $f20,$f14 61 cvt.w.s $f20,$f24 66 div.d $f29,$f20,$f27 102 madd.d $f18,$f19,$f26,$f20 112 mov.d $f20,$f14 139 mul.d $f20,$f20,$f16
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/external/llvm/test/MC/Mips/mips32r2/ |
D | valid.s | 49 ceil.w.s $f6,$f20 60 cvt.w.d $f20,$f14 61 cvt.w.s $f20,$f24 66 div.d $f29,$f20,$f27 102 madd.d $f18,$f19,$f26,$f20 112 mov.d $f20,$f14 139 mul.d $f20,$f20,$f16
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/external/llvm/test/MC/Mips/mips32r5/ |
D | valid.s | 49 ceil.w.s $f6,$f20 60 cvt.w.d $f20,$f14 61 cvt.w.s $f20,$f24 66 div.d $f29,$f20,$f27 103 madd.d $f18,$f19,$f26,$f20 113 mov.d $f20,$f14 140 mul.d $f20,$f20,$f16
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/external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
D | valid-xfail-mips32r2.txt | 18 0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 20 0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 35 0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20 39 0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20 41 0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8 52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20 62 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
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/external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
D | valid-xfail-mips32r5.txt | 18 0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 20 0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 35 0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20 39 0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20 41 0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8 52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20 62 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
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/external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
D | valid-xfail-mips32r3.txt | 18 0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 20 0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 35 0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20 39 0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20 41 0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8 52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20 62 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
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/external/llvm/test/MC/Disassembler/Mips/mips64/ |
D | valid-mips64-xfail.txt | 18 0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 20 0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 36 0x46 0xd4 0x39 0x3e # CHECK: c.le.ps $fcc1, $f7, $f20 40 0x46 0xd4 0x67 0x39 # CHECK: c.ngle.ps $fcc7, $f12, $f20 53 0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20 59 0x46 0xc9 0xcd 0x11 # CHECK: movt.ps $f20, $f25, $fcc2
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/external/llvm/test/MC/Disassembler/Mips/mips1/ |
D | valid-mips1.txt | 77 0x46 0x00 0xc5 0x24 # CHECK: cvt.w.s $f20, $f24 86 0x46 0x20 0x75 0x06 # CHECK: mov.d $f20, $f14 87 0x46 0x20 0x75 0x24 # CHECK: cvt.w.d $f20, $f14 93 0x46 0x30 0xa5 0x02 # CHECK: mul.d $f20, $f20, $f16 94 0x46 0x3a 0xa7 0x03 # CHECK: div.d $f28, $f20, $f26
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D | valid-mips1-el.txt | 37 0x24 0x75 0x20 0x46 # CHECK: cvt.w.d $f20, $f14 38 0x24 0xc5 0x00 0x46 # CHECK: cvt.w.s $f20, $f24 40 0x03 0xa7 0x3a 0x46 # CHECK: div.d $f28, $f20, $f26 59 0x06 0x75 0x20 0x46 # CHECK: mov.d $f20, $f14 69 0x02 0xa5 0x30 0x46 # CHECK: mul.d $f20, $f20, $f16
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/external/llvm/test/MC/Mips/mips3/ |
D | valid.s | 47 ceil.w.s $f6,$f20 58 cvt.w.d $f20,$f14 59 cvt.w.s $f20,$f24 73 div.d $f29,$f20,$f27 143 mov.d $f20,$f14 153 mul.d $f20,$f20,$f16
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/external/llvm/test/MC/Disassembler/Mips/mips2/ |
D | valid-mips2-el.txt | 37 0x8e 0xa1 0x00 0x46 # CHECK: ceil.w.s $f6, $f20 44 0x24 0x75 0x20 0x46 # CHECK: cvt.w.d $f20, $f14 45 0x24 0xc5 0x00 0x46 # CHECK: cvt.w.s $f20, $f24 47 0x03 0xa7 0x3a 0x46 # CHECK: div.d $f28, $f20, $f26 73 0x06 0x75 0x20 0x46 # CHECK: mov.d $f20, $f14 83 0x02 0xa5 0x30 0x46 # CHECK: mul.d $f20, $f20, $f16
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D | valid-mips2.txt | 118 0x46 0x00 0xa1 0x8e # CHECK: ceil.w.s $f6, $f20 119 0x46 0x00 0xc5 0x24 # CHECK: cvt.w.s $f20, $f24 132 0x46 0x20 0x75 0x06 # CHECK: mov.d $f20, $f14 133 0x46 0x20 0x75 0x24 # CHECK: cvt.w.d $f20, $f14 142 0x46 0x30 0xa5 0x02 # CHECK: mul.d $f20, $f20, $f16 143 0x46 0x3a 0xa7 0x03 # CHECK: div.d $f28, $f20, $f26
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/external/llvm/test/CodeGen/Mips/cconv/ |
D | callee-saved-fpxx1.ll | 20 ; O32-FP64-INV-NOT: sdc1 $f20, 21 ; O32-FPXX-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
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/external/valgrind/none/tests/mips32/ |
D | MoveIns.c | 303 TESTINSNMOVE("mfc1 $a3, $f20", 12, f20, a3); in main() 332 TESTINSNMOVEt("mtc1 $a3, $f20", 14, f20, a3); in main() 361 TESTINSNMOVE1s("mov.s $f19, $f20", 12, f19, f20); in main() 362 TESTINSNMOVE1s("mov.s $f20, $f21", 16, f20, f21); in main() 389 TESTINSNMOVE1d("mov.d $f18, $f20", 8, f18, f20); in main() 390 TESTINSNMOVE1d("mov.d $f18, $f20", 16, f18, f20); in main() 391 TESTINSNMOVE1d("mov.d $f20, $f22", 24, f20, f22); in main() 392 TESTINSNMOVE1d("mov.d $f20, $f22", 32, f20, f22); in main()
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/external/llvm/test/CodeGen/PowerPC/ |
D | vsx-spill.ll | 10 …9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f2… 31 …9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f2… 51 …9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f2…
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/external/llvm/test/Transforms/LoopStrengthReduce/ |
D | count-to-zero.ll | 16 %tmp1 = tail call i32 @f20(i32 %c_addr.1) nounwind ; <i32> [#uses=1] 43 declare i32 @f20(i32)
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