Searched refs:getCommonSubClass (Results 1 – 14 of 14) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 430 return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) != nullptr; in hasVGPRs()
432 return getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) != nullptr; in hasVGPRs()
434 return getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) != nullptr; in hasVGPRs()
436 return getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) != nullptr; in hasVGPRs()
438 return getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) != nullptr; in hasVGPRs()
440 return getCommonSubClass(&AMDGPU::VReg_512RegClass, RC) != nullptr; in hasVGPRs()
501 return getCommonSubClass(DefRC, SrcRC) != nullptr; in shouldRewriteCopySrc()
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| D | SILowerI1Copies.cpp | 111 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) { in runOnMachineFunction()
137 } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) && in runOnMachineFunction()
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| D | SIInstrInfo.cpp | 1694 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC)) in legalizeOpWithMove()
1789 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC; in isLegalRegOperand()
2085 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()), in legalizeOperands()
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| /external/llvm/lib/CodeGen/ |
| D | LiveStackAnalysis.cpp | 72 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); in getOrCreateInterval()
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| D | TargetRegisterInfo.cpp | 202 TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A, in getCommonSubClass() function in TargetRegisterInfo
324 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
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| D | MachineRegisterInfo.cpp | 53 getTargetRegisterInfo()->getCommonSubClass(OldRC, RC); in constrainRegClass()
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| D | RegisterCoalescer.cpp | 365 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
961 TRI->getCommonSubClass(DefRC, DstRC); in reMaterializeTrivialDef()
995 NewRC = TRI->getCommonSubClass(NewRC, DefRC); in reMaterializeTrivialDef()
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| D | MachineInstr.cpp | 1162 CurRC = TRI->getCommonSubClass(CurRC, OpRC); in getRegClassConstraintEffect()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 626 getCommonSubClass(const TargetRegisterClass *A,
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 142 TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy); in EmitCopyFromReg()
230 VTRC = TRI->getCommonSubClass(RC, VTRC); in CreateVirtualRegisters()
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| D | DAGCombiner.cpp | 10337 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC)) in canMergeExpensiveCrossRegisterBankCopy()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 701 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
736 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 367 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 4211 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
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