| /external/llvm/lib/Target/Mips/ |
| D | MipsFrameLowering.cpp | 124 unsigned Size = TRI.getMinimalPhysRegClass(*R)->getSize(); in estimateStackSize()
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| D | MipsSEFrameLowering.cpp | 245 unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2; in expandCopyACC()
814 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInfo.cpp | 44 MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(SrcReg); in copyPhysReg()
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| D | WebAssemblyPEI.cpp | 345 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); in assignCalleeSavedSpillSlots()
469 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores()
498 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores()
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| D | WebAssemblyAsmPrinter.cpp | 96 MRI->getTargetRegisterInfo()->getMinimalPhysRegClass(RegNo); in getRegType()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.cpp | 276 const TargetRegisterClass* RC = HRI->getMinimalPhysRegClass(DepReg); in isCallDependent()
588 predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc); in canPromoteToNewValueStore()
600 predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst); in canPromoteToNewValueStore()
1242 RC = HRI->getMinimalPhysRegClass(DepReg); in isLegalToPacketizeTogether()
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| D | HexagonFrameLowering.cpp | 946 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); in insertCSRSpillsInBlock()
995 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); in insertCSRRestoresInBlock()
1278 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg); in assignCalleeSavedSpillSlots()
1290 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R); in assignCalleeSavedSpillSlots()
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| D | HexagonExpandCondsets.cpp | 664 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS); in getCondTfrOpcode()
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| D | BitTracker.cpp | 332 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PhysS); in getRegBitWidth()
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| D | HexagonInstrInfo.cpp | 1109 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg()); in DefinesPredicate()
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| /external/llvm/lib/CodeGen/ |
| D | StackMaps.cpp | 139 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg()); in parseOperand()
233 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize(); in createLiveOutReg()
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| D | PrologEpilogInserter.cpp | 329 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); in assignCalleeSavedSpillSlots()
453 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores()
482 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores()
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| D | TargetRegisterInfo.cpp | 135 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, MVT VT) const { in getMinimalPhysRegClass() function in TargetRegisterInfo
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| D | AggressiveAntiDepBreaker.cpp | 609 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); in FindSuitableFreeRegisters()
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 131 unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8; in AddMachineRegPiece()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreFrameLowering.cpp | 439 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
467 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in restoreCalleeSavedRegisters()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 329 getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const;
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| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 1847 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in assignCalleeSavedSpillSlots()
1894 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
1938 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in restoreCalleeSavedRegisters()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 582 TRI->getMinimalPhysRegClass(Reg, VT); in ListScheduleBottomUp()
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| D | ScheduleDAGSDNodes.cpp | 134 TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo)); in CheckForPhysRegDependency()
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| D | InstrEmitter.cpp | 157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); in EmitCopyFromReg()
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| D | ScheduleDAGRRList.cpp | 1460 TRI->getMinimalPhysRegClass(Reg, VT); in PickNodeToScheduleBottomUp()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 1606 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
1751 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in restoreCalleeSavedRegisters()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 253 // Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 728 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT); in LowerFormalArguments()
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