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Searched refs:hsub (Results 1 – 12 of 12) sorted by relevance

/external/llvm/test/CodeGen/X86/
Dsse3-intrinsics-x86.ll37 …%res = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double…
40 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
45 …%res = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> […
48 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
Dsse_reload_fold.ll20 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>)
27 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>)
81 %t = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %y, <4 x float> %f)
116 %t = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %y, <2 x double> %f)
132 %t = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %f, <2 x double> %y)
Dsse3-intrinsics-fast-isel.ll77 %res = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1)
80 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
92 %res = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1)
95 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
Dstack-folding-fp-avx1.ll909 %2 = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1)
912 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
918 %2 = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %a0, <4 x double> %a1)
921 declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
927 %2 = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1)
930 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
936 %2 = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a0, <8 x float> %a1)
939 declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
Dstack-folding-fp-sse42.ll626 %2 = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1)
629 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
635 %2 = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1)
638 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
Davx-intrinsics-x86.ll1038 …%res = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double…
1041 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
1049 …%res = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> […
1052 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
2511 …%res = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x dou…
2514 declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
2522 …%res = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>…
2525 declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
/external/llvm/lib/CodeGen/
DCalcSpillWeights.cpp49 unsigned sub, hreg, hsub; in copyHint() local
53 hsub = mi->getOperand(1).getSubReg(); in copyHint()
57 hsub = mi->getOperand(0).getSubReg(); in copyHint()
64 return sub == hsub ? hreg : 0; in copyHint()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td1326 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1327 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1329 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1330 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1484 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1488 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
2034 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>;
2035 defm : VecROStoreLane0Pat<ro16, store , v8i16, i16, hsub, STRHroW, STRHroX>;
3368 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3372 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
[all …]
DAArch64InstrInfo.cpp1744 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub, in copyPhysReg()
1746 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub, in copyPhysReg()
1752 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub, in copyPhysReg()
1754 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub, in copyPhysReg()
DAArch64RegisterInfo.td26 def hsub : SubRegIndex<16>;
284 let SubRegIndices = [hsub] in {
DAArch64ISelDAGToDAG.cpp2394 SubReg = AArch64::hsub; in Select()
DAArch64ISelLowering.cpp2014 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)), in LowerBITCAST()
9818 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)), in ReplaceBITCASTResults()