| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrFormats.td | 271 // Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
281 bits<4> imm4;
289 let Inst{3-0} = imm4;
429 // <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
480 // <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
504 // <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
582 // <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
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| /external/vixl/src/vixl/a64/ |
| D | assembler-a64.h | 1992 void clrex(int imm4 = 0xf);
4002 static Instr CRm(int imm4) { in CRm() argument
4003 VIXL_ASSERT(is_uint4(imm4)); in CRm()
4004 return imm4 << CRm_offset; in CRm()
4007 static Instr CRn(int imm4) { in CRn() argument
4008 VIXL_ASSERT(is_uint4(imm4)); in CRn()
4009 return imm4 << CRn_offset; in CRn()
4174 static Instr ImmNEONExt(int imm4) { in ImmNEONExt() argument
4175 VIXL_ASSERT(is_uint4(imm4)); in ImmNEONExt()
4176 return imm4 << ImmNEONExt_offset; in ImmNEONExt()
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| D | disasm-a64.cc | 3077 int imm4 = instr->ImmNEON4(); in SubstituteImmediateField() local
3080 rn_index = imm4 >> tz; in SubstituteImmediateField()
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| D | simulator-a64.cc | 2911 int imm4 = instr->ImmNEON4(); in VisitNEONCopy() local
2912 int rn_index = imm4 >> tz; in VisitNEONCopy()
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| D | assembler-a64.cc | 2555 void Assembler::clrex(int imm4) { in clrex() argument
2556 Emit(CLREX | CRm(imm4)); in clrex()
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| /external/valgrind/VEX/priv/ |
| D | host_arm_isel.c | 3325 UInt imm4; in iselNeon64Expr_wrk() local
3329 imm4 = (index << 1) + 1; in iselNeon64Expr_wrk()
3337 imm4, False in iselNeon64Expr_wrk()
3344 UInt imm4; in iselNeon64Expr_wrk() local
3348 imm4 = (index << 2) + 2; in iselNeon64Expr_wrk()
3356 imm4, False in iselNeon64Expr_wrk()
3363 UInt imm4; in iselNeon64Expr_wrk() local
3367 imm4 = (index << 3) + 4; in iselNeon64Expr_wrk()
3375 imm4, False in iselNeon64Expr_wrk()
3730 UInt imm4; in iselNeon64Expr_wrk() local
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| D | host_arm_defs.h | 247 UShort imm4; member
256 extern ARMRI84* ARMRI84_I84 ( UShort imm8, UShort imm4 );
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| D | host_arm_defs.c | 423 ARMRI84* ARMRI84_I84 ( UShort imm8, UShort imm4 ) { in ARMRI84_I84() argument
427 ri84->ARMri84.I84.imm4 = imm4; in ARMRI84_I84()
429 vassert(imm4 >= 0 && imm4 <= 15); in ARMRI84_I84()
443 2 * ri84->ARMri84.I84.imm4)); in ppARMRI84()
2767 vassert(0 == (ri->ARMri84.I84.imm4 & ~0x0F)); in skeletal_RI84()
2770 instr |= (ri->ARMri84.I84.imm4 << 8); in skeletal_RI84()
4536 UInt imm4 = imm & 0xF; in emit_ARMInstr() local
4571 cmode, BITS4(0,Q,op,1), imm4); in emit_ARMInstr()
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| D | guest_arm64_toIR.c | 8213 UInt imm4 = INSN(14,11); in dis_AdvSIMD_EXT() local
8225 if (imm4 == 0) { in dis_AdvSIMD_EXT()
8228 vassert(imm4 >= 1 && imm4 <= 15); in dis_AdvSIMD_EXT()
8230 mkexpr(sHi), mkexpr(sLo), mkU8(imm4))); in dis_AdvSIMD_EXT()
8233 DIP("ext v%u.16b, v%u.16b, v%u.16b, #%u\n", dd, nn, mm, imm4); in dis_AdvSIMD_EXT()
8235 if (imm4 >= 8) return False; in dis_AdvSIMD_EXT()
8236 if (imm4 == 0) { in dis_AdvSIMD_EXT()
8239 vassert(imm4 >= 1 && imm4 <= 7); in dis_AdvSIMD_EXT()
8244 mkexpr(hi64lo64), mkexpr(hi64lo64), mkU8(imm4))); in dis_AdvSIMD_EXT()
8247 DIP("ext v%u.8b, v%u.8b, v%u.8b, #%u\n", dd, nn, mm, imm4); in dis_AdvSIMD_EXT()
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| D | guest_arm_toIR.c | 2862 UInt imm4 = (theInstr >> 8) & 0xf; in dis_neon_vext() local
2868 /*loV128*/getQReg(nreg), mkU8(imm4)), condT); in dis_neon_vext()
2871 /*loI64*/getDRegI64(nreg), mkU8(imm4)), condT); in dis_neon_vext()
2874 reg_t, mreg, imm4); in dis_neon_vext()
2990 UInt imm4 = (theInstr >> 16) & 0xF; in dis_neon_vdup() local
2997 if ((imm4 == 0) || (imm4 == 8)) in dis_neon_vdup()
3009 if ((imm4 & 1) == 1) { in dis_neon_vdup()
3012 index = imm4 >> 1; in dis_neon_vdup()
3014 } else if ((imm4 & 3) == 2) { in dis_neon_vdup()
3017 index = imm4 >> 2; in dis_neon_vdup()
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| D | host_arm64_defs.c | 5197 UInt imm4 = i->ARM64in.VExtV.amtB; in emit_ARM64Instr() local
5198 vassert(imm4 >= 1 && imm4 <= 15); in emit_ARM64Instr()
5200 X000000 | (imm4 << 1), vN, vD); in emit_ARM64Instr()
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | invalid-armv7.txt | 371 # invalid imm4 value (0b1xxx)
372 # A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED;
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| /external/v8/src/arm/ |
| D | assembler-arm.cc | 2970 int imm4 = (imm5 >> 1) & 0xf; in vcvt_f64_s32() local
2972 vd*B12 | 0x5*B9 | B8 | B7 | B6 | i*B5 | imm4); in vcvt_f64_s32()
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| /external/vixl/doc/ |
| D | supported-instructions.md | 285 void clrex(int imm4 = 0xf)
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 6164 class BaseSIMDMov<bit Q, string size, bits<4> imm4, RegisterClass regtype,
6169 let Inst{14-11} = imm4;
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