| /external/gemmlowp/meta/generators/ |
| D | zip_Nx8_neon.py | 41 lanes = []
45 lanes.append(ZipLane(input_address,
50 lanes.append(ZipLane(address_register,
55 return lanes
67 def GenerateClearAggregators(emitter, lanes): argument
68 for lane in lanes:
72 def GenerateLoadAggregateStore(emitter, lanes, output_address, alignment): argument
77 for lane in lanes:
83 for lane in lanes:
92 emitter, leftovers, lanes, output_address): argument
[all …]
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| D | qnt_Nx8_neon.py | 26 def BuildName(lanes, leftovers, aligned): argument
27 name = 'qnt_%dx8' % lanes
35 def LoadAndDuplicateOffsets(emitter, registers, lanes, offsets): argument
36 if lanes == 1 or lanes == 2 or lanes == 3:
38 for unused_i in range(0, lanes):
47 raise ConfigurationError('Unsupported number of lanes: %d' % lanes)
62 lanes = []
67 lanes.append(QntLane(source,
75 lanes.append(QntLane(input_register,
84 return lanes
[all …]
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| D | mul_Nx8_Mx8_neon.py | 22 self.lanes = []
25 self.lanes.append(lane)
28 for i in range(0, len(self.lanes)):
29 registers.FreeRegister(self.lanes[i])
30 self.lanes[i] = None
34 lanes = MulLanes(address)
36 lanes.AddLane(registers.DoubleRegister())
37 return lanes
41 lanes = MulLanes(address)
42 lanes.AddLane(registers.Low(quad_register))
[all …]
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| /external/v8/test/mjsunit/harmony/ |
| D | simd.js | 25 function isValidSimdString(string, value, type, lanes) { argument
36 if (laneStrings.length !== lanes)
38 for (var i = 0; i < lanes; i++) {
67 function TestConstructor(type, lanes) { argument
82 function TestType(type, lanes) { argument
95 function TestPrototype(type, lanes) { argument
105 function TestValueOf(type, lanes) { argument
116 function TestGet(type, lanes) { argument
127 function TestToBoolean(type, lanes) { argument
146 function TestToString(type, lanes) { argument
[all …]
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| /external/v8/src/runtime/ |
| D | runtime-simd.cc | 211 #define CONVERT_SIMD_LANE_ARG_CHECKED(name, index, lanes) \ argument
213 RUNTIME_ASSERT(name >= 0 && name < lanes);
228 lane_type lanes[kLaneCount]; \
230 lanes[i] = op(a->get_lane(i)); \
232 Handle<type> result = isolate->factory()->New##type(lanes);
239 lane_type lanes[kLaneCount]; \
241 lanes[i] = op(a->get_lane(i), b->get_lane(i)); \
243 Handle<type> result = isolate->factory()->New##type(lanes);
250 bool lanes[kLaneCount]; \
252 lanes[i] = a->get_lane(i) op b->get_lane(i); \
[all …]
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| /external/v8/test/cctest/ |
| D | test-simd.cc | 16 float lanes[lane_count] = {0}; \
17 Handle<type> a = factory->New##type(lanes); \
18 Handle<type> b = factory->New##type(lanes); \
49 lane_type lanes[lane_count] = {0}; \
50 Handle<type> a = factory->New##type(lanes); \
51 Handle<type> b = factory->New##type(lanes); \
82 bool lanes[lane_count] = {false}; \
83 Handle<type> a = factory->New##type(lanes); \
84 Handle<type> b = factory->New##type(lanes); \
|
| /external/v8/test/cctest/heap/ |
| D | test-heap.cc | 256 float lanes[4] = {1, 2, 3, 4}; in TEST() local
260 Handle<Float32x4> value = factory->NewFloat32x4(lanes); in TEST()
262 CheckSimdValue<Float32x4, float, 4>(*value, lanes, 3.14f); in TEST()
276 value = factory->NewFloat32x4(lanes); in TEST()
293 int32_t lanes[4] = {1, 2, 3, 4}; in TEST() local
295 Handle<Int32x4> value = factory->NewInt32x4(lanes); in TEST()
297 CheckSimdValue<Int32x4, int32_t, 4>(*value, lanes, 3); in TEST()
307 uint32_t lanes[4] = {1, 2, 3, 4}; in TEST() local
309 Handle<Uint32x4> value = factory->NewUint32x4(lanes); in TEST()
311 CheckSimdValue<Uint32x4, uint32_t, 4>(*value, lanes, 3); in TEST()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 474 class TypedVecListAsmOperand<int count, int regsize, int lanes, string kind>
476 let Name = "TypedVectorList" # count # "_" # lanes # kind;
479 = "isTypedVectorList<" # count # ", " # lanes # ", '" # kind # "'>";
483 class TypedVecListRegOperand<RegisterClass Reg, int lanes, string kind>
484 : RegisterOperand<Reg, "printTypedVectorList<" # lanes # ", '"
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| D | AArch64Schedule.td | 95 // Read the unwritten lanes of the VLD's destination registers.
|
| D | AArch64CallingConvention.td | 30 // their lanes are in a consistent order.
90 // their lanes are in a consistent order.
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_emit_nv50.cpp | 602 code[1] = 0x00200000 | (i->lanes << 14); in emitLOAD()
619 code[1] = 0x00200000 | (i->lanes << 14); in emitLOAD()
759 code[1] |= (i->lanes << 14); in emitMOV()
1690 emitQUADOP(insn, insn->lanes, insn->subOp); in emitInstruction()
1759 if (i->join || i->lanes != 0xf || i->exit) in getMinEncodingSize()
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| D | nv50_ir.cpp | 573 lanes = 0xf; in init()
737 i->lanes = lanes; in clone()
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| D | nv50_ir_build_util.cpp | 265 quadop->lanes = l; in mkQuadop()
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| D | nv50_ir.h | 696 unsigned lanes : 4; variable
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| /external/vixl/src/vixl/a64/ |
| D | assembler-a64.h | 272 VRegister(unsigned code, unsigned size, unsigned lanes = 1)
273 : CPURegister(code, size, kVRegister), lanes_(lanes) { in CPURegister()
333 int lanes() const { in lanes() function
4081 switch (vd.lanes()) { in VFormat()
4089 switch (vd.lanes()) { in VFormat()
4102 if (vd.lanes() == 1) { in FPFormat()
4109 if (vd.lanes() == 2) { in FPFormat()
4115 VIXL_ASSERT((vd.lanes() == 4) && vd.Is128Bits()); in FPFormat()
4122 switch (vd.lanes()) { in LSVFormat()
4131 switch (vd.lanes()) { in LSVFormat()
[all …]
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| /external/llvm/test/CodeGen/X86/ |
| D | vshift-4.ll | 16 ; shift1b can't use a packed shift but can shift lanes separately and shuffle back together
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| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 78 // - "H" - Halve the number of lanes in the type.
79 // - "D" - Double the number of lanes in the type.
94 // all lanes. The type of the vector is the base type of the intrinsic.
159 // is a width in bits to reverse. The lanes this maps to is determined
164 // mask0 - The initial sequence of lanes for shuffle ARG0
166 // mask0 - The initial sequence of lanes for shuffle ARG1
660 // E.3.16 Extract lanes from a vector
666 // E.3.17 Set lanes within a vector
678 // E.3.19 Set all lanes to same value
1109 // Set all lanes to same value
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| /external/libhevc/common/arm/ |
| D | ihevc_intra_pred_luma_dc.s | 454 vdup.16 q12, d11[0] @3*dc + 2 (moved to all lanes)
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vdiv_combine.ll | 139 ; Don't combine with 8 lanes. Just make sure things don't crash.
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| /external/llvm/docs/ |
| D | BigEndianNEON.rst | 66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering.
109 … ``ST1``. ``LDR`` and ``STR`` are oblivious to the size of the individual lanes of a vector. ``LD1…
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| /external/libvpx/libvpx/vpx_dsp/x86/ |
| D | quantize_avx_x86_64.asm | 61 pcmpeqw m4, m4 ; All word lanes -1
208 pcmpeqw m4, m4 ; All lanes -1
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 2557 One-element single structure load to all lanes.
2584 Two-element single structure load to all lanes.
2614 Three-element single structure load to all lanes.
2647 Four-element single structure load to all lanes.
3818 Two-element single structure store from two lanes.
3837 Three-element single structure store from three lanes.
3858 Four-element single structure store from four lanes.
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | invalid-thumbv7.txt | 259 # A8.6.315 VLD3 (single 3-element structure to all lanes)
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| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| D | nv50_ir_emit_nvc0.cpp | 1508 opc |= i->lanes << 5; in emitMOV()
1720 emitQUADOP(insn, insn->subOp, insn->lanes); in emitInstruction()
1780 if (i->op == OP_MOV && i->lanes != 0xf) { in getMinEncodingSize()
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| /external/v8/src/ |
| D | factory.h | 359 Handle<Type> New##Type(lane_type lanes[lane_count], \
|