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/external/llvm/test/CodeGen/Hexagon/
Dremove_lsr.ll4 ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
5 ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
8 ; r17:16 = lsr(r11:10, #32)
11 ; r17:16 = lsr(r11:10, #32)
13 ; This makes the lsr instruction dead and it gets removed subsequently
32 %lsr.iv42 = phi i32 [ %lsr.iv.next, %for.body ], [ 2, %entry ]
33 %lsr.iv40 = phi i8* [ %scevgep41, %for.body ], [ %scevgep39, %entry ]
34 %lsr.iv37 = phi i8* [ %scevgep38, %for.body ], [ %scevgep36, %entry ]
35 %lsr.iv33 = phi %union.vect32* [ %scevgep34, %for.body ], [ %scevgep32, %entry ]
36 %lsr.iv29 = phi %union.vect32* [ %scevgep30, %for.body ], [ %scevgep28, %entry ]
[all …]
Dhwloop2.ll1 ; RUN: llc -disable-lsr -march=hexagon < %s | FileCheck %s
20 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ %n, %for.body.lr.ph ]
21 %lsr.iv1 = phi i32* [ %scevgep, %for.body ], [ %a, %for.body.lr.ph ]
22 %1 = load i32, i32* %lsr.iv1, align 4
26 %lsr.iv.next = add i32 %lsr.iv, -1
27 %scevgep = getelementptr i32, i32* %lsr.iv1, i32 1
28 %cmp = icmp eq i32 %lsr.iv.next, 0
Dpostinc-load.ll11 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ 10, %entry ]
22 %lsr.iv.next = add i32 %lsr.iv, -1
23 %exitcond = icmp eq i32 %lsr.iv.next, 0
Dpostinc-store.ll11 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ 10, %entry ]
23 %lsr.iv.next = add i32 %lsr.iv, -1
24 %exitcond = icmp eq i32 %lsr.iv.next, 0
/external/valgrind/none/tests/arm/
Dv6intThumb.stdout.exp2149 adds.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000…
2150 adds.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000…
2151 adds.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000…
2152 adds.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000…
2161 add.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000…
2162 add.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000…
2163 add.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000…
2164 add.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000…
2173 adds.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000…
2174 adds.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000…
[all …]
/external/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/
Dlsr-postinc-pos-addrspace.ll1 ; RUN: llc -march=amdgcn -mcpu=bonaire -print-lsr-output < %s 2>&1 | FileCheck %s
10 ; CHECK: %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb ], [ -2, %entry ]
11 ; CHECK: %lsr.iv = phi i32 [ %lsr.iv.next, %bb ], [ undef, %entry ]
14 ; CHECK: %lsr.iv.next = add i32 %lsr.iv, -1
15 ; CHECK: %lsr.iv.next2 = add i32 %lsr.iv1, 2
16 ; CHECK: %scevgep = getelementptr i8, i8 addrspace(3)* %t, i32 %lsr.iv.next2
40 ; CHECK: %lsr.iv.next = add i64 %lsr.iv, -1
41 ; CHECK: %lsr.iv.next2 = add i64 %lsr.iv1, 2
42 ; CHECK: %scevgep = getelementptr i8, i8 addrspace(1)* %t, i64 %lsr.iv.next2
65 ; CHECK: %p = getelementptr i8, i8 addrspace(1)* %t, i32 %lsr.iv1
[all …]
/external/llvm/test/Analysis/BasicAA/
Dphi-spec-order.ll17 …%lsr.iv4 = phi [16000 x double]* [ %i11, %for.body4 ], [ bitcast (double* getelementptr inbounds (…
19 %lsr.iv1 = phi [16000 x double]* [ %i10, %for.body4 ], [ @X, %for.cond2.preheader ]
21 ; CHECK: NoAlias:{{[ \t]+}}[16000 x double]* %lsr.iv1, [16000 x double]* %lsr.iv4
23 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body4 ], [ 16000, %for.cond2.preheader ]
24 %lsr.iv46 = bitcast [16000 x double]* %lsr.iv4 to <4 x double>*
25 %lsr.iv12 = bitcast [16000 x double]* %lsr.iv1 to <4 x double>*
26 %scevgep11 = getelementptr <4 x double>, <4 x double>* %lsr.iv46, i64 -2
29 store <4 x double> %add, <4 x double>* %lsr.iv12, align 32
30 %scevgep10 = getelementptr <4 x double>, <4 x double>* %lsr.iv46, i64 -1
33 %scevgep9 = getelementptr <4 x double>, <4 x double>* %lsr.iv12, i64 1
[all …]
/external/llvm/test/CodeGen/X86/
Dfast-isel-trunc-kill-subreg.ll21 %lsr.iv3 = phi i64 [ %lsr.iv.next4, %bb241 ], [ %tmp12, %bb ]
22 %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb241 ], [ 0, %bb ]
23 %lsr.iv.next2 = add nuw nsw i32 %lsr.iv1, 1
24 %lsr.iv.next4 = add i64 %lsr.iv3, 32
25 %exitcond = icmp eq i32 %lsr.iv.next2, 8
33 %lsr.iv = phi i32 [ %lsr.iv.next, %bb270 ], [ %tmp18, %.preheader.preheader ]
34 %lsr.iv.next = add i32 %lsr.iv, 4
35 %tmp272 = icmp slt i32 %lsr.iv.next, 100
Dragreedy-bug.ll49 %lsr.iv27 = phi i64 [ %lsr.iv.next28, %if.end17 ], [ 0, %if.end ]
50 %scevgep55 = getelementptr i8, i8* %4, i64 %lsr.iv27
71 %sunkaddr58 = add i64 %sunkaddr, %lsr.iv27
93 %sunkaddr61 = add i64 %sunkaddr60, %lsr.iv27
97 %sunkaddr64 = add i64 %sunkaddr63, %lsr.iv27
103 %lsr.iv.next28 = add i64 %lsr.iv27, 1
117 %sunkaddr70 = add i64 %sunkaddr69, %lsr.iv27
128 %sunkaddr73 = add i64 %sunkaddr72, %lsr.iv27
138 %scevgep53 = getelementptr i8, i8* %scevgep52, i64 %lsr.iv27
146 %scevgep48 = getelementptr i8, i8* %scevgep47, i64 %lsr.iv27
[all …]
/external/llvm/test/MC/ARM/
Darm_addrmode2.s5 @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
9 @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
13 @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
17 @ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]
21 ldrt r1, [r0], r2, lsr #3
25 ldrbt r1, [r0], r2, lsr #3
29 strt r1, [r0], r2, lsr #3
33 strbt r1, [r0], r2, lsr #3
38 @ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7]
39 @ CHECK: ldrb r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xf0,0xe7]
[all …]
Darm-shift-encoding.s4 ldr r0, [r0, r0, lsr #32]
5 ldr r0, [r0, r0, lsr #16]
14 @ CHECK: ldr r0, [r0, r0, lsr #32] @ encoding: [0x20,0x00,0x90,0xe7]
15 @ CHECK: ldr r0, [r0, r0, lsr #16] @ encoding: [0x20,0x08,0x90,0xe7]
24 pld [r0, r0, lsr #32]
25 pld [r0, r0, lsr #16]
34 @ CHECK: [r0, r0, lsr #32] @ encoding: [0x20,0xf0,0xd0,0xf7]
35 @ CHECK: [r0, r0, lsr #16] @ encoding: [0x20,0xf8,0xd0,0xf7]
44 str r0, [r0, r0, lsr #32]
45 str r0, [r0, r0, lsr #16]
[all …]
Dthumb-shift-encoding.s8 sbc.w r1, r8, r9, lsr #32
9 sbc.w r2, r7, r10, lsr #16
18 @ CHECK: sbc.w r1, r8, r9, lsr #32 @ encoding: [0x68,0xeb,0x19,0x01]
19 @ CHECK: sbc.w r2, r7, r10, lsr #16 @ encoding: [0x67,0xeb,0x1a,0x42]
28 and.w r1, r8, r9, lsr #32
29 and.w r2, r7, r10, lsr #16
38 @ CHECK: and.w r1, r8, r9, lsr #32 @ encoding: [0x08,0xea,0x19,0x01]
39 @ CHECK: and.w r2, r7, r10, lsr #16 @ encoding: [0x07,0xea,0x1a,0x42]
Dbasic-arm-instructions.s72 adc r4, r5, r6, lsr #1
73 adc r4, r5, r6, lsr #31
74 adc r4, r5, r6, lsr #32
83 adc r6, r7, r8, lsr r9
92 adc r4, r5, lsr #1
93 adc r4, r5, lsr #31
94 adc r4, r5, lsr #32
102 adc r6, r7, lsr r9
111 @ CHECK: adc r4, r5, r6, lsr #1 @ encoding: [0xa6,0x40,0xa5,0xe0]
112 @ CHECK: adc r4, r5, r6, lsr #31 @ encoding: [0xa6,0x4f,0xa5,0xe0]
[all …]
/external/llvm/test/MC/AArch64/
Darm64-logical-encoding.s54 and w1, w2, w3, lsr #2
55 and x1, x2, x3, lsr #2
65 ; CHECK: and w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x0a]
66 ; CHECK: and x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0x8a]
76 ands w1, w2, w3, lsr #2
77 ands x1, x2, x3, lsr #2
87 ; CHECK: ands w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x6a]
88 ; CHECK: ands x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0xea]
98 bic w1, w2, w3, lsr #3
99 bic x1, x2, x3, lsr #3
[all …]
Dbasic-a64-diagnostics.s184 add wsp, w1, w2, lsr #3
199 add w1, w2, w3, lsr #-1
200 add w1, w2, w3, lsr #32
205 add x1, x2, x3, lsr #-1
206 add x1, x2, x3, lsr #64
248 adds w1, w2, w3, lsr #-1
249 adds w1, w2, w3, lsr #32
254 adds x1, x2, x3, lsr #-1
255 adds x1, x2, x3, lsr #64
297 sub w1, w2, w3, lsr #-1
[all …]
/external/boringssl/linux-arm/crypto/aes/
Daes-armv4.S236 mov r4,r0,lsr#24 @ write output in endian-neutral
237 mov r5,r0,lsr#16 @ manner...
238 mov r6,r0,lsr#8
241 mov r4,r1,lsr#24
243 mov r5,r1,lsr#16
245 mov r6,r1,lsr#8
248 mov r4,r2,lsr#24
250 mov r5,r2,lsr#16
252 mov r6,r2,lsr#8
255 mov r4,r3,lsr#24
[all …]
/external/boringssl/linux-arm/crypto/modes/
Dghash-armv4.S59 eor r4,r8,r4,lsr#4
63 eor r5,r9,r5,lsr#4
65 eor r6,r10,r6,lsr#4
67 eor r7,r11,r7,lsr#4
79 eor r4,r8,r4,lsr#4
81 eor r5,r9,r5,lsr#4
84 eor r6,r10,r6,lsr#4
87 eor r7,r11,r7,lsr#4
94 eor r4,r8,r4,lsr#4
97 eor r5,r9,r5,lsr#4
[all …]
/external/llvm/test/MC/Disassembler/Hexagon/
Dxtype_shift.txt8 # CHECK: r17:16 = lsr(r21:20, #31)
14 # CHECK: r17 = lsr(r21, #31)
22 # CHECK: r17:16 -= lsr(r21:20, #31)
28 # CHECK: r17:16 += lsr(r21:20, #31)
34 # CHECK: r17 -= lsr(r21, #31)
40 # CHECK: r17 += lsr(r21, #31)
48 # CHECK: r17 = add(#21, lsr(r17, #23))
50 # CHECK: r17 = sub(#21, lsr(r17, #23))
60 # CHECK: r17:16 &= lsr(r21:20, #31)
66 # CHECK: r17:16 |= lsr(r21:20, #31)
[all …]
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_shift.ll15 declare i64 @llvm.hexagon.S2.lsr.i.p(i64, i32)
17 %z = call i64 @llvm.hexagon.S2.lsr.i.p(i64 %a, i32 0)
20 ; CHECK: = lsr({{.*}}, #0)
36 declare i32 @llvm.hexagon.S2.lsr.i.r(i32, i32)
38 %z = call i32 @llvm.hexagon.S2.lsr.i.r(i32 %a, i32 0)
41 ; CHECK: = lsr({{.*}}, #0)
58 declare i64 @llvm.hexagon.S2.lsr.i.p.nac(i64, i64, i32)
60 %z = call i64 @llvm.hexagon.S2.lsr.i.p.nac(i64 %a, i64 %b, i32 0)
63 ; CHECK: -= lsr({{.*}}, #0)
79 declare i64 @llvm.hexagon.S2.lsr.i.p.acc(i64, i64, i32)
[all …]
/external/llvm/test/CodeGen/AArch64/
Dragreedy-csr.ll54 %lsr.iv27 = phi i64 [ %lsr.iv.next28, %if.end17 ], [ 0, %if.end ]
55 %scevgep55 = getelementptr i8, i8* %4, i64 %lsr.iv27
76 %sunkaddr58 = add i64 %sunkaddr, %lsr.iv27
98 %sunkaddr61 = add i64 %sunkaddr60, %lsr.iv27
102 %sunkaddr64 = add i64 %sunkaddr63, %lsr.iv27
108 %lsr.iv.next28 = add i64 %lsr.iv27, 1
122 %sunkaddr70 = add i64 %sunkaddr69, %lsr.iv27
133 %sunkaddr73 = add i64 %sunkaddr72, %lsr.iv27
143 %scevgep53 = getelementptr i8, i8* %scevgep52, i64 %lsr.iv27
151 %scevgep48 = getelementptr i8, i8* %scevgep47, i64 %lsr.iv27
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-logical.txt64 # CHECK: and w1, w2, w3, lsr #2
65 # CHECK: and x1, x2, x3, lsr #2
86 # CHECK: ands w1, w2, w3, lsr #2
87 # CHECK: ands x1, x2, x3, lsr #2
108 # CHECK: bic w1, w2, w3, lsr #3
109 # CHECK: bic x1, x2, x3, lsr #3
130 # CHECK: bics w1, w2, w3, lsr #3
131 # CHECK: bics x1, x2, x3, lsr #3
152 # CHECK: eon w1, w2, w3, lsr #4
153 # CHECK: eon x1, x2, x3, lsr #4
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dstdux-constuse.ll1 ; RUN: llc -mcpu=a2 -disable-lsr < %s | FileCheck %s
15 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body4 ], [ 16000, %for.cond2.preheader ]
25 %lsr.iv.next = add i32 %lsr.iv, -16
26 %exitcond.15 = icmp eq i32 %lsr.iv.next, 0
/external/llvm/test/CodeGen/ARM/
Darm-and-tst-peephole.ll20 %lsr.iv2 = phi %struct.Foo* [ %scevgep3, %sw.bb ], [ %scevgep, %entry ]
21 %lsr.iv = phi i32 [ %lsr.iv.next, %sw.bb ], [ 1, %entry ]
23 %lsr.iv24 = bitcast %struct.Foo* %lsr.iv2 to i8**
24 %scevgep5 = getelementptr i8*, i8** %lsr.iv24, i32 -1
64 %lsr.iv.next = add i32 %lsr.iv, 1
65 %scevgep3 = getelementptr %struct.Foo, %struct.Foo* %lsr.iv2, i32 1
69 ret %struct.Foo* %lsr.iv2
72 %tmp1 = add i32 %acc.tr, %lsr.iv
/external/llvm/test/Transforms/LoopStrengthReduce/
D2011-12-19-PostincQuadratic.ll14 ; CHECK: %lsr.iv1 = phi [121 x i32]*
16 ; CHECK: %lsr.iv = phi i32
18 ; CHECK: %scevgep = getelementptr i1, i1* %{{.*}}, i32 %lsr.iv
20 ; CHECK: %lsr.iv3 = phi [121 x i32]* [ %lsr.iv1, %for.body43.preheader ]
Dlsr-expand-quadratic.ll13 ; CHECK: %lsr.iv = phi i32 [ %lsr.iv.next, %test2.loop ], [ -16777216, %entry ]
14 ; CHECK: %lsr.iv.next = add nsw i32 %lsr.iv, 16777216
18 ; CHECK: %sext.us = mul i32 %lsr.iv.next, %sub.cond.us

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