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/external/opencv/cvaux/src/
Dcvvideo.cpp53 CvMat odd_stub, *odd = (CvMat*)fieldOdd; in cvDeInterlace() local
59 CV_CALL( odd = cvGetMat( odd, &odd_stub )); in cvDeInterlace()
61 if( !CV_ARE_TYPES_EQ( frame, even ) || !CV_ARE_TYPES_EQ( frame, odd )) in cvDeInterlace()
64 if( frame->cols != even->cols || frame->cols != odd->cols || in cvDeInterlace()
65 frame->rows != even->rows*2 || odd->rows != even->rows ) in cvDeInterlace()
75 memcpy( odd->data.ptr + even->step*y, in cvDeInterlace()
/external/llvm/test/MC/Mips/
Dupdate-module-level-options.s6 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers
14 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
Dset-oddspreg-nooddspreg-error.s6 # CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
Dnooddspreg-error.s9 # CHECK-ERROR: :[[@LINE-1]]:15: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK-ERROR: :[[@LINE-2]]:25: error: -mno-odd-spreg prohibits the use of odd FPU registers
/external/eigen/Eigen/src/Geometry/
DEulerAngles.h48 const Index odd = ((a0+1)%3 == a1) ? 0 : 1; in eulerAngles() local
50 const Index j = (a0 + 1 + odd)%3; in eulerAngles()
51 const Index k = (a0 + 2 - odd)%3; in eulerAngles()
56 if((odd && res[0]<Scalar(0)) || ((!odd) && res[0]>Scalar(0))) in eulerAngles()
86 if((odd && res[0]<Scalar(0)) || ((!odd) && res[0]>Scalar(0))) { in eulerAngles()
96 if (!odd) in eulerAngles()
/external/clang/test/Analysis/
DNewDelete-path-notes.cpp23 void test(Odd *odd) { in test() argument
24 odd->kill(); // expected-note{{Calling 'Odd::kill'}} in test()
26 delete odd; // expected-warning {{Attempt to free released memory}} in test()
/external/pdfium/third_party/zlib_v128/
Dcrc32.c363 unsigned long odd[GF2_DIM]; /* odd-power-of-two zeros operator */ in crc32_combine_() local
370 odd[0] = 0xedb88320UL; /* CRC-32 polynomial */ in crc32_combine_()
373 odd[n] = row; in crc32_combine_()
378 gf2_matrix_square(even, odd); in crc32_combine_()
381 gf2_matrix_square(odd, even); in crc32_combine_()
387 gf2_matrix_square(even, odd); in crc32_combine_()
397 gf2_matrix_square(odd, even); in crc32_combine_()
399 crc1 = gf2_matrix_times(odd, crc1); in crc32_combine_()
/external/zlib/src/
Dcrc32.c363 unsigned long odd[GF2_DIM]; /* odd-power-of-two zeros operator */ local
370 odd[0] = 0xedb88320UL; /* CRC-32 polynomial */
373 odd[n] = row;
378 gf2_matrix_square(even, odd);
381 gf2_matrix_square(odd, even);
387 gf2_matrix_square(even, odd);
397 gf2_matrix_square(odd, even);
399 crc1 = gf2_matrix_times(odd, crc1);
/external/opencv3/3rdparty/zlib/
Dcrc32.c363 unsigned long odd[GF2_DIM]; /* odd-power-of-two zeros operator */ local
370 odd[0] = 0xedb88320UL; /* CRC-32 polynomial */
373 odd[n] = row;
378 gf2_matrix_square(even, odd);
381 gf2_matrix_square(odd, even);
387 gf2_matrix_square(even, odd);
397 gf2_matrix_square(odd, even);
399 crc1 = gf2_matrix_times(odd, crc1);
/external/llvm/test/CodeGen/Mips/
Dno-odd-spreg-msa.ll12 ; Force the float into an odd-numbered register using named registers and
19 ; The intention is that if odd single precision registers are permitted, the
23 ; On the other hand, if odd single precision registers are not permitted, it
46 ; Force the float into an odd-numbered register using named registers and
53 ; The intention is that if odd single precision registers are permitted, the
57 ; On the other hand, if odd single precision registers are not permitted, it
85 ; The intention is that if odd single precision registers are permitted, the
88 ; On the other hand, if odd single precision registers are not permitted, it
113 ; The intention is that if odd single precision registers are permitted, the
116 ; On the other hand, if odd single precision registers are not permitted, it
/external/selinux/secilc/docs/
Dcil_xen_statements.md25 <tr class="odd">
35 <tr class="odd">
65 <tr class="odd">
75 <tr class="odd">
105 <tr class="odd">
113 <tr class="odd">
143 <tr class="odd">
151 <tr class="odd">
181 <tr class="odd">
189 <tr class="odd">
Dcil_user_statements.md21 <tr class="odd">
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99 <tr class="odd">
135 <tr class="odd">
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193 <tr class="odd">
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239 <tr class="odd">
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[all …]
Dcil_role_statements.md21 <tr class="odd">
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67 <tr class="odd">
101 <tr class="odd">
137 <tr class="odd">
145 <tr class="odd">
201 <tr class="odd">
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[all …]
Dcil_conditional_statements.md21 <tr class="odd">
29 <tr class="odd">
66 <tr class="odd">
74 <tr class="odd">
88 <tr class="odd">
135 <tr class="odd">
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Dcil_container_statements.md24 <tr class="odd">
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Dcil_type_statements.md21 <tr class="odd">
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97 <tr class="odd">
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166 <tr class="odd">
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Dcil_class_and_permission_statements.md21 <tr class="odd">
29 <tr class="odd">
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67 <tr class="odd">
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Dcil_mls_labeling_statements.md23 <tr class="odd">
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Dcil_file_labeling_statements.md21 <tr class="odd">
29 <tr class="odd">
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46 <tr class="odd">
54 <tr class="odd">
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70 <tr class="odd">
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[all …]
Dcil_default_object_statements.md23 <tr class="odd">
31 <tr class="odd">
75 <tr class="odd">
83 <tr class="odd">
122 <tr class="odd">
130 <tr class="odd">
160 <tr class="odd">
168 <tr class="odd">
Dcil_access_vector_rules.md21 <tr class="odd">
29 <tr class="odd">
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198 <tr class="odd">
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Dcil_network_labeling_statements.md27 <tr class="odd">
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/external/icu/icu4c/source/test/intltest/
Dtestidna.cpp996 UChar odd[MAX_DEST_SIZE]; in testChaining() local
1009 memcpy(odd,expected,(expectedLen+1) * U_SIZEOF_UCHAR); in testChaining()
1013 evenLen = func(odd,-1,even,MAX_DEST_SIZE,options, &parseError, &status); in testChaining()
1019 oddLen = func(even,-1,odd,MAX_DEST_SIZE,options, &parseError, &status); in testChaining()
1028 u_strCaseCompare(odd,oddLen, expected,expectedLen, 0, &status) !=0 ){ in testChaining()
1034 u_strncmp(odd,expected,expectedLen) !=0 ){ in testChaining()
1046 memcpy(odd,expected,(expectedLen+1) * U_SIZEOF_UCHAR); in testChaining()
1050 … evenLen = func(odd,-1,even,MAX_DEST_SIZE,options|UIDNA_ALLOW_UNASSIGNED, &parseError, &status); in testChaining()
1056 … oddLen = func(even,-1,odd,MAX_DEST_SIZE,options|UIDNA_ALLOW_UNASSIGNED, &parseError, &status); in testChaining()
1065 u_strCaseCompare(odd,oddLen, expected,expectedLen, 0, &status) !=0 ){ in testChaining()
[all …]
/external/emma/core/java12/com/vladium/emma/report/html/
DReportGenerator.java282 boolean odd = true; in visit()
284 for (Iterator packages = item.getChildren (order); packages.hasNext (); odd = ! odd) in visit()
300 addItemRow (pkg, odd, childSummaryTable, headerColumns, childHREF, false); in visit()
399 boolean odd = true; in visit()
401 … for (Iterator srcORclsFiles = item.getChildren (order); srcORclsFiles.hasNext (); odd = ! odd) in visit()
417 addItemRow (srcORcls, odd, childSummaryTable, headerColumns, childHREF, false); in visit()
559 boolean odd = false; in visit()
561 … for (Iterator methods = cls.getChildren (order2); methods.hasNext (); odd = ! odd) in visit()
580 … addClassItemRow (method, odd, childSummaryTable, headerColumns, HREFname, createAnchors); in visit()
691 boolean odd = true; in visit()
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-compare-instructions.ll158 ; Using registers other than v0, v1 are possible, but would be odd.
167 ; Using registers other than v0, v1 are possible, but would be odd.
176 ; Using registers other than v0, v1 are possible, but would be odd.
185 ; Using registers other than v0, v1 are possible, but would be odd.
194 ; Using registers other than v0, v1 are possible, but would be odd.
203 ; Using registers other than v0, v1 are possible, but would be odd.
212 ; Using registers other than v0, v1 are possible, but would be odd.
270 ; Using registers other than v0, v1 are possible, but would be odd.
279 ; Using registers other than v0, v1 are possible, but would be odd.
288 ; Using registers other than v0, v1 are possible, but would be odd.
[all …]

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