| /external/lzma/Asm/x86/ |
| D | XzCrc64Opt.asm | 11 rN equ r10 define
16 SRCDAT equ rN + rD
29 dec rN
36 mov rN, num_VAR
39 test rN, rN
47 cmp rN, 8
49 add rN, rD
50 mov num_VAR, rN
51 sub rN, 4
52 and rN, NOT 3
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| D | 7zCrcOpt.asm | 9 rN equ r7 define
21 SRCDAT equ rN + rD + 4 *
42 dec rN
49 mov rN, num_VAR
51 test rN, rN
59 cmp rN, 16
61 add rN, rD
62 mov num_VAR, rN
63 sub rN, 8
64 and rN, NOT 7
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| /external/valgrind/VEX/priv/ |
| D | guest_arm_toIR.c | 2369 IRExpr* mk_EA_reg_plusminus_imm12 ( UInt rN, UInt bU, UInt imm12, in mk_EA_reg_plusminus_imm12() argument
2372 vassert(rN < 16); in mk_EA_reg_plusminus_imm12()
2376 DIS(buf, "[r%u, #%c%u]", rN, opChar, imm12); in mk_EA_reg_plusminus_imm12()
2379 getIRegA(rN), in mk_EA_reg_plusminus_imm12()
2388 IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM, in mk_EA_reg_plusminus_shifted_reg() argument
2392 vassert(rN < 16); in mk_EA_reg_plusminus_shifted_reg()
2403 DIS(buf, "[r%u, %c r%u LSL #%u]", rN, opChar, rM, imm5); in mk_EA_reg_plusminus_shifted_reg()
2413 rN, opChar, rM, imm5 == 0 ? 32 : imm5); in mk_EA_reg_plusminus_shifted_reg()
2425 rN, opChar, rM, imm5 == 0 ? 32 : imm5); in mk_EA_reg_plusminus_shifted_reg()
2436 DIS(buf, "[r%u, %cr%u, RRX]", rN, opChar, rM); in mk_EA_reg_plusminus_shifted_reg()
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| D | host_arm64_defs.c | 1013 ARM64Instr* ARM64Instr_VLdStH ( Bool isLoad, HReg sD, HReg rN, UInt uimm12 ) { in ARM64Instr_VLdStH() argument
1018 i->ARM64in.VLdStH.rN = rN; in ARM64Instr_VLdStH()
1023 ARM64Instr* ARM64Instr_VLdStS ( Bool isLoad, HReg sD, HReg rN, UInt uimm12 ) { in ARM64Instr_VLdStS() argument
1028 i->ARM64in.VLdStS.rN = rN; in ARM64Instr_VLdStS()
1033 ARM64Instr* ARM64Instr_VLdStD ( Bool isLoad, HReg dD, HReg rN, UInt uimm12 ) { in ARM64Instr_VLdStD() argument
1038 i->ARM64in.VLdStD.rN = rN; in ARM64Instr_VLdStD()
1043 ARM64Instr* ARM64Instr_VLdStQ ( Bool isLoad, HReg rQ, HReg rN ) { in ARM64Instr_VLdStQ() argument
1048 i->ARM64in.VLdStQ.rN = rN; in ARM64Instr_VLdStQ()
1575 ppHRegARM64(i->ARM64in.VLdStH.rN); in ppARM64Instr()
1580 ppHRegARM64(i->ARM64in.VLdStH.rN); in ppARM64Instr()
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| D | host_arm64_defs.h | 681 HReg rN; member
688 HReg rN; member
695 HReg rN; member
702 HReg rN; // address member
912 extern ARM64Instr* ARM64Instr_VLdStH ( Bool isLoad, HReg sD, HReg rN,
914 extern ARM64Instr* ARM64Instr_VLdStS ( Bool isLoad, HReg sD, HReg rN,
916 extern ARM64Instr* ARM64Instr_VLdStD ( Bool isLoad, HReg dD, HReg rN,
918 extern ARM64Instr* ARM64Instr_VLdStQ ( Bool isLoad, HReg rQ, HReg rN );
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| D | host_arm_defs.c | 365 ARMAModeN *mkARMAModeN_RR ( HReg rN, HReg rM ) { in mkARMAModeN_RR() argument
368 am->ARMamN.RR.rN = rN; in mkARMAModeN_RR()
373 ARMAModeN *mkARMAModeN_R ( HReg rN ) { in mkARMAModeN_R() argument
376 am->ARMamN.R.rN = rN; in mkARMAModeN_R()
382 addHRegUse(u, HRmRead, am->ARMamN.R.rN); in addRegUsage_ARMAModeN()
384 addHRegUse(u, HRmRead, am->ARMamN.RR.rN); in addRegUsage_ARMAModeN()
391 am->ARMamN.R.rN = lookupHRegRemap(m, am->ARMamN.R.rN); in mapRegs_ARMAModeN()
393 am->ARMamN.RR.rN = lookupHRegRemap(m, am->ARMamN.RR.rN); in mapRegs_ARMAModeN()
401 ppHRegARM(am->ARMamN.R.rN); in ppARMAModeN()
403 ppHRegARM(am->ARMamN.RR.rN); in ppARMAModeN()
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| D | host_arm_defs.h | 215 HReg rN; member
219 HReg rN; member
944 HReg rN; member
1017 extern ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 );
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| D | host_arm64_isel.c | 2189 HReg rN = iselIntExpr_R(env, e->Iex.Load.addr); in iselV128Expr_wrk() local
2191 addInstr(env, ARM64Instr_VLdStQ(True/*isLoad*/, res, rN)); in iselV128Expr_wrk()
3036 HReg rN = get_baseblock_register(); in iselDblExpr_wrk() local
3037 addInstr(env, ARM64Instr_VLdStD(True/*isLoad*/, rD, rN, offs)); in iselDblExpr_wrk()
3223 HReg rN = get_baseblock_register(); in iselFltExpr_wrk() local
3224 addInstr(env, ARM64Instr_VLdStS(True/*isLoad*/, rD, rN, offs)); in iselFltExpr_wrk()
3370 HReg rN = get_baseblock_register(); in iselF16Expr_wrk() local
3371 addInstr(env, ARM64Instr_VLdStH(True/*isLoad*/, rD, rN, offs)); in iselF16Expr_wrk()
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| D | guest_arm64_toIR.c | 2814 UInt rN = INSN(9,5); in dis_ARM64_data_processing_register() local
2823 assign(argL, getIRegOrZR(is64, rN)); in dis_ARM64_data_processing_register()
2834 nameIRegOrZR(is64, rD), nameIRegOrZR(is64, rN), in dis_ARM64_data_processing_register()
2856 UInt rN = INSN(9,5); in dis_ARM64_data_processing_register() local
2869 assign(argL, getIRegOrZR(is64, rN)); in dis_ARM64_data_processing_register()
2897 nameIRegOrZR(is64, rD), nameIRegOrZR(is64, rN), in dis_ARM64_data_processing_register()
2922 UInt rN = INSN(9,5); in dis_ARM64_data_processing_register() local
2930 assign(argL, getIRegOrZR(is64, rN)); in dis_ARM64_data_processing_register()
2951 if (rN == 31/*zr*/ && sh == 0/*LSL*/ && imm6 == 0 && bN == 0) { in dis_ARM64_data_processing_register()
2956 nameIRegOrZR(is64, rD), nameIRegOrZR(is64, rN), in dis_ARM64_data_processing_register()
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| /external/compiler-rt/lib/builtins/arm/ |
| D | sync-ops.h | 51 #define MINMAX_4(rD, rN, rM, cmp_kind) \ argument
52 cmp rN, rM ; \
55 mov##cmp_kind rD, rN
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| D | sync_fetch_and_nand_4.S | 17 #define nand_4(rD, rN, rM) bic rD, rN, rM argument
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| D | sync_fetch_and_xor_4.S | 17 #define xor_4(rD, rN, rM) eor rD, rN, rM argument
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| D | sync_fetch_and_add_4.S | 18 #define add_4(rD, rN, rM) add rD, rN, rM argument
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| D | sync_fetch_and_sub_4.S | 18 #define sub_4(rD, rN, rM) sub rD, rN, rM argument
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| D | sync_fetch_and_and_4.S | 17 #define and_4(rD, rN, rM) and rD, rN, rM argument
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| D | sync_fetch_and_or_4.S | 17 #define or_4(rD, rN, rM) orr rD, rN, rM argument
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| D | sync_fetch_and_umin_4.S | 17 #define umin_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lo) argument
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| D | sync_fetch_and_max_4.S | 17 #define max_4(rD, rN, rM) MINMAX_4(rD, rN, rM, gt) argument
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| D | sync_fetch_and_min_4.S | 17 #define min_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lt) argument
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| D | sync_fetch_and_umax_4.S | 17 #define umax_4(rD, rN, rM) MINMAX_4(rD, rN, rM, hi) argument
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| /external/llvm/test/CodeGen/ARM/ |
| D | varargs-spill-stack-align-nacl.ll | 9 ; stack. A varargs function must therefore spill rN-r3 just below the
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| /external/valgrind/docs/internals/ |
| D | 3_9_BUGSTATUS.txt | 29 335618 arm(thumb): unhanded instruction: mov.w rN, pc/sp
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| /external/libvpx/libvpx/third_party/libyuv/source/ |
| D | x86inc.asm | 127 ; rN and rNq are the native-size register holding function argument N
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| /external/scrypt/patches/ |
| D | arm-neon.patch | 262 + * temporary storage V must be 128rN bytes in length; the temporary storage
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 232 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
|