Searched refs:raddhn (Results 1 – 18 of 18) sorted by relevance
80 define <8 x i16> @raddhn(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %b0, <4 x i32> %b1) nounwind readn…81 ; CHECK-LABEL: raddhn:83 ; CHECK: raddhn.4h v0, v0, v186 …%vraddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a0, <4 x i32> %a1) no…87 …%vraddhn2.i10 = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %b0, <4 x i32> %b1) …142 declare <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
67 ;CHECK: raddhn.8b70 %tmp3 = call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)76 ;CHECK: raddhn.4h79 %tmp3 = call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)85 ;CHECK: raddhn.2s88 %tmp3 = call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)94 ;CHECK: raddhn.8b96 …%vraddhn2.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwi…97 …%vraddhn_high2.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b) n…104 ;CHECK: raddhn.4h[all …]
47 declare <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64>, <2 x i64>)49 declare <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>)51 declare <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16>, <8 x i16>)691 ; CHECK: raddhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h693 %vraddhn2.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b)699 ; CHECK: raddhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s701 %vraddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a, <4 x i32> %b)707 ; CHECK: raddhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d709 %vraddhn2.i = tail call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %a, <2 x i64> %b)715 ; CHECK: raddhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h[all …]
385 raddhn v0.8b, v1.8h, v2.8h386 raddhn v0.4h, v1.4s, v2.4s387 raddhn v0.2s, v1.2d, v2.2d
2791 raddhn v0.8b, v1.8h, v2.8b2792 raddhn v0.4h, v1.4s, v2.4h2793 raddhn v0.2s, v1.2d, v2.2s
242 raddhn v12.4h, v0.4s, v8.4s252 raddhn v12.4h, v0.4s, v8.4s262 raddhn v12.4h, v0.4s, v8.4s272 raddhn v12.4h, v0.4s, v8.4s282 raddhn v12.4h, v0.4s, v8.4s292 raddhn v12.4h, v0.4s, v8.4s302 raddhn v12.4h, v0.4s, v8.4s312 raddhn v12.4h, v0.4s, v8.4s
1444 # CHECK: raddhn v0.8b, v1.8h, v2.8h1445 # CHECK: raddhn v0.4h, v1.4s, v2.4s1446 # CHECK: raddhn v0.2s, v1.2d, v2.2d
2728 GEN_BINARY_TEST(raddhn, 2s, 2d, 2d)2730 GEN_BINARY_TEST(raddhn, 4h, 4s, 4s)2732 GEN_BINARY_TEST(raddhn, 8b, 8h, 8h)
26959 raddhn v9.2s, v7.2d, v8.2d afbfc85e0c1c48334ea1524a0ade5200 79487a40a5dfbc0cb0537f133e68f917 000…26961 raddhn v9.4h, v7.4s, v8.4s df28535a766ecc147823af2632098729 6a45a6db9a685742f5028d2d94cc5d5a 000…26963 raddhn v9.8b, v7.8h, v8.8h a51d242dcced68587d6bcf2a3b0a82f7 86fd3e4bb26cd1f8ebe5c4ab42948c9f 000…
2154 V(raddhn) \
2151 V(raddhn, Raddhn) \
3567 void raddhn(const VRegister& vd,
2745 case NEON_RADDHN: raddhn(vf, rd, rn, rm); break; in VisitNEON3Different()
3329 LogicVRegister Simulator::raddhn(VectorFormat vform, in raddhn() function in vixl::Simulator
2445 V(raddhn, NEON_RADDHN, vd.IsD()) \
3844 DEFINE_TEST_NEON_3DIFF_NARROW(raddhn, Basic)
2860 void raddhn(const VRegister& vd,
3426 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;