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Searched refs:s_mov_b64 (Results 1 – 13 of 13) sorted by relevance

/external/llvm/test/MC/AMDGPU/
Dsop1-err.s23 s_mov_b64 s1, s[0:1] label
26 s_mov_b64 s[0:1], s1 label
34 s_mov_b64 s[0:1], 0xfffffffff label
37 s_mov_b64 s[0:1], 0xfffffffff label
40 s_mov_b64 s[0:1], 0xfffffffff label
43 s_mov_b64 s[0:1], 0x0000000200000000 label
59 s_mov_b64 s[102:103], -1 label
Dsop1.s21 s_mov_b64 s[2:3], s[4:5] label
24 s_mov_b64 s[2:3], 0xffffffffffffffff label
27 s_mov_b64 s[2:3], 0xffffffff label
30 s_mov_b64 s[0:1], 0x80000000 label
33 s_mov_b64 s[102:103], -1 label
52 s_mov_b64 s[2:3], s[4:5] label
Dflat-scratch.s10 s_mov_b64 flat_scratch, -1 label
26 s_mov_b64 flat_scratch_lo, -1 label
29 s_mov_b64 flat_scratch_hi, -1 label
Dout-of-range-registers.s16 s_mov_b64 s[0:17], -1 label
19 s_mov_b64 s[103:104], -1 label
22 s_mov_b64 s[104:105], -1 label
/external/llvm/test/CodeGen/AMDGPU/
Dvalu-i1.ll8 ; SI-NOT: s_mov_b64 s[{{[0-9]:[0-9]}}], -1
77 ; SI: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
121 ; SI: s_mov_b64 [[ZERO:s\[[0-9]+:[0-9]+\]]], 0{{$}}
122 ; SI: s_mov_b64 [[COND_STATE:s\[[0-9]+:[0-9]+\]]], [[ZERO]]
Dllvm.amdgpu.kilp.ll5 ; SI: s_mov_b64 exec, 0
Dsi-annotate-cf.ll30 ; SI: s_mov_b64 [[ZERO:s\[[0-9]+:[0-9]+\]]], 0
Dllvm.AMDGPU.kill.ll6 ; SI: s_mov_b64 exec, 0
Dllvm.AMDGPU.div_fmas.ll90 ; SI: s_mov_b64 vcc, 0
99 ; SI: s_mov_b64 vcc, -1
Doperand-folding.ll40 ; CHECK-NOT: s_mov_b64
Dsalu-to-valu.ll16 ; Make sure we aren't using VGPRs for the source operand of s_mov_b64
17 ; GCN-NOT: s_mov_b64 s[{{[0-9]+:[0-9]+}}], v
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td207 // Requires 2 s_mov_b64 to copy
212 // Requires 4 s_mov_b64 to copy
217 // Requires 8 s_mov_b64 to copy
DSIInstructions.td107 defm S_MOV_B64 : SOP1_64 <sop1<0x04, 0x01>, "s_mov_b64", []>;