| /external/llvm/test/MC/AArch64/ |
| D | arm64-bitfield-encoding.s | 14 sbfiz wzr, w0, #31, #1
15 sbfiz xzr, x0, #31, #1
25 ; CHECK: sbfiz wzr, w0, #31, #1 ; encoding: [0x1f,0x00,0x01,0x13]
26 ; CHECK: sbfiz xzr, x0, #31, #1 ; encoding: [0x1f,0x00,0x61,0x93]
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| D | basic-a64-diagnostics.s | 887 sbfiz w1, w2, #0, #0
888 sbfiz wsp, w9, #0, #1
889 sbfiz w9, w10, #32, #1
890 sbfiz w11, w12, #32, #0
891 sbfiz w9, w10, #10, #23
892 sbfiz x3, x5, #12, #53
893 sbfiz sp, x3, #7, #6
894 sbfiz w3, wsp, #10, #8
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| D | arm64-aliases.s | 180 sbfiz w0, w0, #1, #4
181 sbfiz x0, x0, #1, #4
195 ; CHECK: sbfiz w0, w0, #1, #4
196 ; CHECK: sbfiz x0, x0, #1, #4
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| D | basic-a64-instructions.s | 1031 sbfiz w9, w10, #0, #1
1032 sbfiz x2, x3, #63, #1
1033 sbfiz x19, x20, #0, #64
1034 sbfiz x9, x10, #5, #59
1035 sbfiz w9, w10, #0, #32
1036 sbfiz w11, w12, #31, #1
1037 sbfiz w13, w14, #29, #3
1038 sbfiz xzr, xzr, #10, #11
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-shifted-sext.ll | 9 ; CHECK: sbfiz w0, [[REG]], #4, #8
33 ; CHECK: sbfiz w0, [[REG]], #8, #8
58 ; CHECK: sbfiz w0, [[REG]], #4, #8
80 ; CHECK: sbfiz w0, [[REG]], #8, #8
103 ; CHECK: sbfiz x0, x[[REG]], #4, #8
125 ; CHECK: sbfiz x0, x[[REG]], #8, #8
148 ; CHECK: sbfiz w0, [[REG]], #4, #16
193 ; CHECK: sbfiz x0, x[[REG]], #4, #16
215 ; CHECK: sbfiz x0, x[[REG]], #16, #16
238 ; CHECK: sbfiz x0, x[[REG]], #4, #32
|
| D | fast-isel-shift.ll | 104 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
120 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
136 ; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #1
168 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
184 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
200 ; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #8
232 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #16
248 ; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #8, #16
278 ; CHECK: sbfiz {{x[0-9]+}}, {{x[0-9]+}}, #16, #32
|
| D | xbfiz.ll | 5 ; CHECK: sbfiz x0, x0, #1, #16
13 ; CHECK: sbfiz w0, w0, #1, #14
|
| D | fast-isel-addressing-modes.ll | 568 ; CHECK: sbfiz [[REG:x[0-9]+]], {{x[0-9]+}}, #3, #32
|
| /external/v8/test/cctest/ |
| D | test-disasm-arm64.cc | 552 COMPARE(sbfiz(w1, w2, 1, 20), "sbfiz w1, w2, #1, #20"); in TEST_()
553 COMPARE(sbfiz(x3, x4, 2, 19), "sbfiz x3, x4, #2, #19"); in TEST_()
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | basic-a64-instructions.txt | 679 # CHECK: sbfiz x2, x3, #63, #1
681 # CHECK: sbfiz x9, x10, #5, #59
683 # CHECK: sbfiz w11, w12, #31, #1
684 # CHECK: sbfiz w13, w14, #29, #3
685 # CHECK: sbfiz xzr, xzr, #10, #11
|
| /external/v8/src/arm64/ |
| D | macro-assembler-arm64-inl.h | 1051 sbfiz(rd, rn, lsb, width); in Sbfiz()
|
| D | assembler-arm64.h | 1153 void sbfiz(const Register& rd, const Register& rn, int lsb, int width) { in sbfiz() function
|
| /external/vixl/src/vixl/a64/ |
| D | macro-assembler-a64.h | 1732 sbfiz(rd, rn, lsb, width); in Sbfiz()
|
| D | assembler-a64.h | 1468 void sbfiz(const Register& rd, in sbfiz() function
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 1011 void sbfiz(const Register& rd,
|
| /external/vixl/test/ |
| D | test-disasm-a64.cc | 562 COMPARE(sbfiz(w1, w2, 1, 20), "sbfiz w1, w2, #1, #20"); in TEST()
563 COMPARE(sbfiz(x3, x4, 2, 19), "sbfiz x3, x4, #2, #19"); in TEST()
|