/external/llvm/test/CodeGen/AArch64/ |
D | fp16-v16-instructions.ll | 6 ; CHECK-DAG: scvtf [[S0:v[0-9]+\.4s]], v0.4s 7 ; CHECK-DAG: scvtf [[S1:v[0-9]+\.4s]], v1.4s 8 ; CHECK-DAG: scvtf [[S2:v[0-9]+\.4s]], v2.4s 9 ; CHECK-DAG: scvtf [[S3:v[0-9]+\.4s]], v3.4s 24 ; CHECK-DAG: scvtf [[D0:v[0-9]+\.2d]], v0.2d 25 ; CHECK-DAG: scvtf [[D1:v[0-9]+\.2d]], v1.2d 26 ; CHECK-DAG: scvtf [[D2:v[0-9]+\.2d]], v2.2d 27 ; CHECK-DAG: scvtf [[D3:v[0-9]+\.2d]], v3.2d 28 ; CHECK-DAG: scvtf [[D4:v[0-9]+\.2d]], v4.2d 29 ; CHECK-DAG: scvtf [[D5:v[0-9]+\.2d]], v5.2d [all …]
|
D | complex-int-to-fp.ll | 4 ; CHECK: scvtf 16 ; CHECK-NEXT: scvtf.2d v0, [[VAL64]] 36 ; CHECK: scvtf.2d v0, [[VAL64]] 57 ; CHECK: scvtf.2d v0, [[VAL64]] 75 ; CHECK: scvtf.2d [[VAL64:v[0-9]+]], v0 94 ; CHECK: scvtf.2s v0, [[VAL32]] 113 ; CHECK: scvtf.2s v0, [[VAL32]] 131 ; CHECK: scvtf.4s v0, [[VAL32]] 151 ; CHECK: scvtf.4s v0, [[VAL32]]
|
D | arm64-scvt.ll | 9 ; CHECK: scvtf s0, s0 29 ; CHECK: scvtf d0, d0 50 ; CHECK: scvtf d0, [[REG]] 411 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] 415 ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]] 429 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] 442 ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] 456 ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], x[[REGNUM]] 472 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] 476 ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]] [all …]
|
D | fcvt-fixed.ll | 110 ; CHECK: scvtf {{s[0-9]+}}, {{w[0-9]+}}, #7 115 ; CHECK: scvtf {{s[0-9]+}}, {{w[0-9]+}}, #32 120 ; CHECK: scvtf {{s[0-9]+}}, {{x[0-9]+}}, #7 125 ; CHECK: scvtf {{s[0-9]+}}, {{x[0-9]+}}, #64 130 ; CHECK: scvtf {{d[0-9]+}}, {{w[0-9]+}}, #7 135 ; CHECK: scvtf {{d[0-9]+}}, {{w[0-9]+}}, #32 140 ; CHECK: scvtf {{d[0-9]+}}, {{x[0-9]+}}, #7 145 ; CHECK: scvtf {{d[0-9]+}}, {{x[0-9]+}}, #64
|
D | fdiv_combine.ll | 5 ; CHECK: scvtf.2s v0, v0, #4 27 ; CHECK: scvtf.2s v0, v0 40 ; CHECK: scvtf.2s v0, v0 53 ; CHECK: scvtf.2s v0, v0, #32 64 ; CHECK: scvtf.4s v0, v0, #2 87 ; CHECK: scvtf.4s v0, v0, #2
|
D | fcvt-int.ll | 69 ; CHECK-DAG: scvtf [[SIG:s[0-9]+]], {{w[0-9]+}} 83 ; CHECK-DAG: scvtf [[SIG:d[0-9]+]], {{w[0-9]+}} 97 ; CHECK-DAG: scvtf [[SIG:s[0-9]+]], {{x[0-9]+}} 111 ; CHECK-DAG: scvtf [[SIG:d[0-9]+]], {{x[0-9]+}}
|
D | arm64-setcc-int-to-fp-combine.ll | 20 ; CHECK: scvtf.2d 21 ; CHECK: scvtf.2d
|
D | arm64-vcvt_n.ll | 13 ; CHECK: scvtf.2s v0, v0, #12 29 ; CHECK: scvtf.4s v0, v0, #30
|
D | fp16-v8-instructions.ll | 262 ; CHECK-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]] 263 ; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]] 276 ; CHECK-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]] 277 ; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]] 288 ; CHECK-DAG: scvtf [[OP1:v[0-9]+\.4s]], v0.4s 289 ; CHECK-DAG: scvtf [[OP2:v[0-9]+\.4s]], v1.4s 300 ; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d 301 ; CHECK-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d
|
D | arm64-vcvt_f32_su32.ll | 14 ; CHECK: scvtf.2s v0, v0 30 ; CHECK: scvtf.4s v0, v0
|
D | arm64-fast-isel-conversion.ll | 242 ; CHECK: scvtf s0, w0 252 ; CHECK: scvtf s0, w0 269 ; CHECK: scvtf s0, w0 278 ; CHECK: scvtf s0, x0 287 ; CHECK: scvtf d0, w0 296 ; CHECK: scvtf d0, x0
|
D | arm64-extend-int-to-fp.ll | 15 ; CHECK-NEXT: scvtf.4s v0, v0
|
D | arm64-fixed-point-scalar-cvt-dagcombine.ll | 8 ; CHECK: scvtf.2d [[REG:v[0-9]+]], v0, #9
|
D | fpconv-vector-op-scalarize.ll | 11 ; CHECK-NEXT: scvtf d0, [[GPR]]
|
D | fp16-v4-instructions.ll | 138 ; CHECK-NEXT: scvtf [[OP4:v[0-9]+\.4s]], [[OP3]] 149 ; CHECK-NEXT: scvtf [[OP2:v[0-9]+\.4s]], [[OP1]] 159 ; CHECK-NEXT: scvtf [[OP1:v[0-9]+\.4s]], v0.4s 168 ; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d 169 ; CHECK-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d
|
D | arm64-fast-isel-noconvert.ll | 16 ; CHECK: scvtf.2d v0, [[EXT]]
|
/external/llvm/test/MC/AArch64/ |
D | neon-scalar-cvt.s | 9 scvtf h23, h14 10 scvtf s22, s13 11 scvtf d21, d12 33 scvtf h22, h13, #16 34 scvtf s22, s13, #32 35 scvtf d21, d12, #64
|
D | arm64-fp-encoding.s | 466 scvtf h1, w2 467 scvtf h1, w2, #1 468 scvtf s1, w2 469 scvtf s1, w2, #1 470 scvtf d1, w2 define 471 scvtf d1, w2, #1 define 472 scvtf h1, x2 473 scvtf h1, x2, #1 474 scvtf s1, x2 475 scvtf s1, x2, #1 [all …]
|
D | neon-simd-shift.s | 403 scvtf v0.4h, v1.4h, #3 404 scvtf v0.8h, v1.8h, #3 405 scvtf v0.2s, v1.2s, #3 406 scvtf v0.4s, v1.4s, #3 407 scvtf v0.2d, v1.2d, #3
|
D | neon-simd-misc.s | 682 scvtf v4.4h, v0.4h 683 scvtf v6.8h, v8.8h 684 scvtf v6.4s, v8.4s 685 scvtf v6.2d, v8.2d 686 scvtf v4.2s, v0.2s
|
D | basic-a64-instructions.s | 2009 scvtf s23, w19, #1 2010 scvtf s31, wzr, #20 2011 scvtf s14, w0, #32 2016 scvtf s23, x19, #1 2017 scvtf s31, xzr, #20 2018 scvtf s14, x0, #64 2023 scvtf d23, w19, #1 2024 scvtf d31, wzr, #20 2025 scvtf d14, w0, #32 2030 scvtf d23, x19, #1 [all …]
|
D | basic-a64-diagnostics.s | 1721 scvtf w13, s31, #0 1722 scvtf w19, s20, #33 1723 scvtf wsp, s19, #14 1734 scvtf x13, s31, #0 1735 scvtf x19, s20, #65 1736 scvtf sp, s19, #14 1810 scvtf s6, wsp
|
D | neon-diagnostics.s | 2039 scvtf v0.2s, v1.2d, #3 2040 scvtf v0.4s, v1.4h, #3 2041 scvtf v0.2d, v1.2s, #3 5203 scvtf s22, s13, #0 5204 scvtf s22, s13, #33 5205 scvtf d21, d12, #65 5206 scvtf d21, s12, #31 5953 scvtf v0.16b, v31.16b 5954 scvtf v2.8h, v4.8h 5955 scvtf v1.8b, v9.8b [all …]
|
/external/v8/test/cctest/ |
D | test-disasm-arm64.cc | 1533 COMPARE(scvtf(d24, w25), "scvtf d24, w25"); in TEST_() 1534 COMPARE(scvtf(s24, w25), "scvtf s24, w25"); in TEST_() 1535 COMPARE(scvtf(d26, x0), "scvtf d26, x0"); in TEST_() 1536 COMPARE(scvtf(s26, x0), "scvtf s26, x0"); in TEST_() 1543 COMPARE(scvtf(d1, x2, 1), "scvtf d1, x2, #1"); in TEST_() 1544 COMPARE(scvtf(s1, x2, 1), "scvtf s1, x2, #1"); in TEST_() 1545 COMPARE(scvtf(d3, x4, 15), "scvtf d3, x4, #15"); in TEST_() 1546 COMPARE(scvtf(s3, x4, 15), "scvtf s3, x4, #15"); in TEST_() 1547 COMPARE(scvtf(d5, x6, 32), "scvtf d5, x6, #32"); in TEST_() 1548 COMPARE(scvtf(s5, x6, 32), "scvtf s5, x6, #32"); in TEST_()
|
/external/llvm/test/MC/Disassembler/AArch64/ |
D | basic-a64-instructions.txt | 1604 # FP16: scvtf h23, w19, #1 1605 # FP16: scvtf h31, wzr, #20 1606 # FP16: scvtf h14, w0, #32 1611 # FP16: scvtf h23, x19, #1 1612 # FP16: scvtf h31, xzr, #20 1613 # FP16: scvtf h14, x0, #64 1618 # CHECK: scvtf s23, w19, #1 1619 # CHECK: scvtf s31, wzr, #20 1620 # CHECK: scvtf s14, w0, #32 1625 # CHECK: scvtf s23, x19, #1 [all …]
|