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Searched refs:setRegClass (Results 1 – 10 of 10) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DSILowerI1Copies.cpp93 MRI.setRegClass(Reg, &AMDGPU::SReg_64RegClass); in runOnMachineFunction()
149 MRI.setRegClass(Reg, &AMDGPU::VGPR_32RegClass); in runOnMachineFunction()
DSIFixSGPRCopies.cpp204 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
DSIISelLowering.cpp2358 MRI.setRegClass(VReg, RC); in AdjustInstrPostInstrSelection()
/external/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp40 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() function in MachineRegisterInfo
58 setRegClass(Reg, NewRC); in constrainRegClass()
83 setRegClass(Reg, NewRC); in recomputeRegClass()
DMachineLICM.cpp1284 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]); in EliminateCSE()
DRegisterCoalescer.cpp998 MRI->setRegClass(DstReg, NewRC); in reMaterializeTrivialDef()
1413 MRI->setRegClass(CP.getDstReg(), CP.getNewRC()); in joinCopy()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUInstrInfo.cpp254 MRI.setRegClass(MO.getReg(), newRegClass); in convertToISA()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp410 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); in PPCComputeAddress()
1206 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1210 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
1223 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1232 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
2297 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); in fastEmitInst_ri()
2299 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass); in fastEmitInst_ri()
/external/llvm/include/llvm/CodeGen/
DMachineRegisterInfo.h562 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp630 MRI->setRegClass(NewVReg, SRC); in EmitRegSequence()