| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrAtomics.td | 55 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
56 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
70 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
71 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
85 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
86 (LDURWi GPR64sp:$Rn, simm9:$offset)>;
100 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
101 (LDURXi GPR64sp:$Rn, simm9:$offset)>;
141 (am_unscaled8 GPR64sp:$Rn, simm9:$offset), GPR32:$val),
142 (STURBBi GPR32:$val, GPR64sp:$Rn, simm9:$offset)>;
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| D | AArch64InstrInfo.td | 1638 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1641 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1644 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1647 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1650 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1653 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1656 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1661 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1665 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1669 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
[all …]
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| D | AArch64InstrFormats.td | 216 // simm9 predicate - True if the immediate is in the range [-256, 255].
221 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
3025 (ins GPR64sp:$Rn, simm9:$offset), asm, pattern>,
3036 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3048 (ins prfop:$Rt, GPR64sp:$Rn, simm9:$offset),
3084 (ins GPR64sp:$Rn, simm9:$offset), asm>,
3095 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3133 (ins GPR64sp:$Rn, simm9:$offset), asm,
3142 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3145 (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
[all …]
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| /external/valgrind/VEX/priv/ |
| D | host_arm64_defs.c | 212 ARM64AMode* ARM64AMode_RI9 ( HReg reg, Int simm9 ) { in ARM64AMode_RI9() argument
216 am->ARM64am.RI9.simm9 = simm9; in ARM64AMode_RI9()
217 vassert(-256 <= simm9 && simm9 <= 255); in ARM64AMode_RI9()
246 vex_printf("%d(", am->ARM64am.RI9.simm9); in ppARM64AMode()
3056 Int simm9 = am->ARM64am.RI9.simm9; in do_load_or_store8() local
3057 vassert(-256 <= simm9 && simm9 <= 255); in do_load_or_store8()
3059 simm9 & 0x1FF, X00, in do_load_or_store8()
3105 Int simm9 = am->ARM64am.RI9.simm9; in do_load_or_store16() local
3106 vassert(-256 <= simm9 && simm9 <= 255); in do_load_or_store16()
3108 simm9 & 0x1FF, X00, in do_load_or_store16()
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| D | host_arm_defs.h | 171 Int simm9; /* -255 .. 255 */ member
181 extern ARMAMode2* ARMAMode2_RI ( HReg reg, Int simm9 );
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| D | host_arm64_defs.h | 130 Int simm9; /* -256 .. +255 */ member
145 extern ARM64AMode* ARM64AMode_RI9 ( HReg reg, Int simm9 );
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| D | host_arm_defs.c | 273 ARMAMode2* ARMAMode2_RI ( HReg reg, Int simm9 ) { in ARMAMode2_RI() argument
277 am->ARMam2.RI.simm9 = simm9; in ARMAMode2_RI()
278 vassert(-255 <= simm9 && simm9 <= 255); in ARMAMode2_RI()
292 vex_printf("%d(", am->ARMam2.RI.simm9); in ppARMAMode2()
3120 if (am->ARMam2.RI.simm9 < 0) { in emit_ARMInstr()
3122 simm8 = -am->ARMam2.RI.simm9; in emit_ARMInstr()
3125 simm8 = am->ARMam2.RI.simm9; in emit_ARMInstr()
3167 if (am->ARMam2.RI.simm9 < 0) { in emit_ARMInstr()
3169 simm8 = -am->ARMam2.RI.simm9; in emit_ARMInstr()
3172 simm8 = am->ARMam2.RI.simm9; in emit_ARMInstr()
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| D | guest_arm64_toIR.c | 4725 Long simm9 = (Long)sx_to_64(imm9, 9); in dis_ARM64_load_store() local
4726 assign(tEA, binop(Iop_Add64, mkexpr(tRN), mkU64(simm9))); in dis_ARM64_load_store()
4753 = wBack && simm9 < 0 && szB == 8 in dis_ARM64_load_store()
4786 nameIReg64orSP(nn), simm9); in dis_ARM64_load_store()
5101 ULong simm9 = sx_to_64(imm9, 9); in dis_ARM64_load_store() local
5104 assign(tEA, binop(Iop_Add64, mkexpr(tRN), mkU64(simm9))); in dis_ARM64_load_store()
5145 ch, nameIRegOrZR(is64, tt), nameIReg64orSP(nn), simm9); in dis_ARM64_load_store()
5177 ULong simm9 = sx_to_64(imm9, 9); in dis_ARM64_load_store() local
5180 assign(tEA, binop(Iop_Add64, mkexpr(tRN), mkU64(simm9))); in dis_ARM64_load_store()
5219 ch, nameIRegOrZR(is64, tt), nameIReg64orSP(nn), (Long)simm9); in dis_ARM64_load_store()
[all …]
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| D | host_arm64_isel.c | 822 && am->ARM64am.RI9.simm9 >= -256 in sane_AMode()
823 && am->ARM64am.RI9.simm9 <= 255 ); in sane_AMode()
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| D | host_arm_isel.c | 811 && am->ARMam2.RI.simm9 >= -255 in sane_AMode2()
812 && am->ARMam2.RI.simm9 <= 255 ); in sane_AMode2()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.td | 492 def simm9 : Operand<i32>;
668 let MIOperandInfo = (ops ptr_rc, simm9);
674 let MIOperandInfo = (ops ptr_rc, simm9);
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| D | MicroMipsInstrInfo.td | 106 let MIOperandInfo = (ops GPR32, simm9);
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| /external/valgrind/none/tests/arm64/ |
| D | memory.stdout.exp | 6 LDUR,STUR (immediate, simm9) (STR cases and wb check are MISSING)
10 LDUR,STUR (immediate, simm9): STR cases are MISSINGLDP,STP (immediate, simm7) (STR cases and wb che…
341 LDUR,STUR (immediate, simm9)
|