| /external/libjpeg-turbo/simd/ |
| D | Makefile.am | 7 jccolext-sse2.asm jcgryext-sse2.asm jdcolext-sse2.asm jdmrgext-sse2.asm \
8 jccolext-sse2-64.asm jcgryext-sse2-64.asm jdcolext-sse2-64.asm \
9 jdmrgext-sse2-64.asm
15 jccolor-sse2-64.asm jcgray-sse2-64.asm jcsample-sse2-64.asm \
16 jdcolor-sse2-64.asm jdmerge-sse2-64.asm jdsample-sse2-64.asm \
17 jfdctfst-sse2-64.asm jfdctint-sse2-64.asm jidctflt-sse2-64.asm \
18 jidctfst-sse2-64.asm jidctint-sse2-64.asm jidctred-sse2-64.asm \
19 jquantf-sse2-64.asm jquanti-sse2-64.asm
21 jccolor-sse2-64.lo: jccolext-sse2-64.asm
22 jcgray-sse2-64.lo: jcgryext-sse2-64.asm
[all …]
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| D | CMakeLists.txt | 24 set(SIMD_BASENAMES jfdctflt-sse-64 jccolor-sse2-64 jcgray-sse2-64
25 jcsample-sse2-64 jdcolor-sse2-64 jdmerge-sse2-64 jdsample-sse2-64
26 jfdctfst-sse2-64 jfdctint-sse2-64 jidctflt-sse2-64 jidctfst-sse2-64
27 jidctint-sse2-64 jidctred-sse2-64 jquantf-sse2-64 jquanti-sse2-64)
33 jidctflt-sse jquant-sse jccolor-sse2 jcgray-sse2 jcsample-sse2 jdcolor-sse2
34 jdmerge-sse2 jdsample-sse2 jfdctfst-sse2 jfdctint-sse2 jidctflt-sse2
35 jidctfst-sse2 jidctint-sse2 jidctred-sse2 jquantf-sse2 jquanti-sse2)
|
| /external/libjpeg-turbo/ |
| D | Android.mk | 38 simd/jsimd_i386.c simd/jccolor-mmx.asm simd/jccolor-sse2.asm \
39 simd/jcgray-mmx.asm simd/jcgray-sse2.asm simd/jcsample-mmx.asm \
40 simd/jcsample-sse2.asm simd/jdcolor-mmx.asm simd/jdcolor-sse2.asm \
41 simd/jdmerge-mmx.asm simd/jdmerge-sse2.asm simd/jdsample-mmx.asm \
42 simd/jdsample-sse2.asm simd/jfdctflt-3dn.asm simd/jfdctflt-sse.asm \
43 simd/jfdctfst-mmx.asm simd/jfdctfst-sse2.asm simd/jfdctint-mmx.asm \
44 simd/jfdctint-sse2.asm simd/jidctflt-3dn.asm simd/jidctflt-sse2.asm \
45 simd/jidctflt-sse.asm simd/jidctfst-mmx.asm simd/jidctfst-sse2.asm \
46 simd/jidctint-mmx.asm simd/jidctint-sse2.asm simd/jidctred-mmx.asm \
47 simd/jidctred-sse2.asm simd/jquant-3dn.asm simd/jquantf-sse2.asm \
[all …]
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| /external/llvm/test/CodeGen/X86/ |
| D | sse2-intrinsics-x86.ll | 1 ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=-avx,+sse2 | FileCheck %s --check-prefix=CHECK --…
6 …%res = call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>…
9 declare <2 x double> @llvm.x86.sse2.add.sd(<2 x double>, <2 x double>) nounwind readnone
14 …%res = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x d…
17 declare <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double>, <2 x double>, i8) nounwind readnone
22 …%res = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x d…
25 declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8) nounwind readnone
32 %res = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
35 declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readnone
42 %res = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
[all …]
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| D | vec_shift5.ll | 1 ; RUN: llc -march=x86-64 -mattr=+sse2 < %s | FileCheck %s
8 …%1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> <i16 1, i16 2, i16 4, i16 8, i16 1, i16 …
17 …%1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> <i16 4, i16 8, i16 16, i16 32, i16 4, i1…
26 …%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> <i16 4, i16 8, i16 16, i16 32, i16 4, i1…
35 %1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> <i32 1, i32 2, i32 4, i32 8>, i32 3)
44 %1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> <i32 4, i32 8, i32 16, i32 32>, i32 3)
53 %1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> <i32 4, i32 8, i32 16, i32 32>, i32 3)
62 %1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> <i64 1, i64 2>, i32 3)
71 %1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> <i64 8, i64 16>, i32 3)
80 …%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> <i16 15, i16 8, i16 undef, i16 undef, i1…
[all …]
|
| D | pic-load-remat.ll | 1 ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -relocation-model=pic | grep psllw | grep pb
8 …%tmp4403 = tail call <8 x i16> @llvm.x86.sse2.psubs.w( <8 x i16> zeroinitializer, <8 x i16> zeroin…
9 …%tmp4443 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> zeroinitializer, <8 x i16> zeroin…
10 …%tmp4609 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> zeroinitializer, <8 x i16> bitcast…
12 …%tmp4658 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp4651, <8 x i16> bitcast (<4 x …
13 …%tmp4669 = tail call <8 x i16> @llvm.x86.sse2.pavg.w( <8 x i16> < i16 -23170, i16 -23170, i16 -231…
14 …%tmp4679 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4669, <8 x i16> %tmp4669 ) no…
16 …%tmp4700 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4689, <8 x i16> zeroinitializ…
19 …%tmp4779 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp4772, <8 x i16> bitcast (<4 x …
21 …%tmp4821 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4810, <8 x i16> zeroinitializ…
[all …]
|
| D | sse2-intrinsics-x86-upgrade.ll | 1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=pentium4 -mattr=sse2 | FileCheck %s
5 %res = call <2 x i64> @llvm.x86.sse2.psll.dq.bs(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
8 declare <2 x i64> @llvm.x86.sse2.psll.dq.bs(<2 x i64>, i32) nounwind readnone
13 %res = call <2 x i64> @llvm.x86.sse2.psrl.dq.bs(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
16 declare <2 x i64> @llvm.x86.sse2.psrl.dq.bs(<2 x i64>, i32) nounwind readnone
20 %res = call <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64> %a0, i32 8) ; <<2 x i64>> [#uses=1]
23 declare <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64>, i32) nounwind readnone
28 %res = call <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64> %a0, i32 8) ; <<2 x i64>> [#uses=1]
31 declare <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64>, i32) nounwind readnone
|
| D | vec_shift3.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psllq
2 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psraw
3 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd | count 2
7 …%tmp3 = tail call <2 x i64> @llvm.x86.sse2.pslli.q( <2 x i64> %x1, i32 %bits ) nounwind readnone …
13 …%tmp3 = tail call <2 x i64> @llvm.x86.sse2.pslli.q( <2 x i64> %x1, i32 10 ) nounwind readnone ; …
20 …%tmp4 = tail call <8 x i16> @llvm.x86.sse2.psrai.w( <8 x i16> %tmp2, i32 %bits ) nounwind readnone…
25 declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32) nounwind readnone
26 declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) nounwind readnone
|
| D | vec_shift.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psllw
2 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psrlq
3 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psraw
9 …%tmp9 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp8, <8 x i16> %tmp6 ) nounwind rea…
19 …%tmp9 = tail call <8 x i16> @llvm.x86.sse2.psra.w( <8 x i16> %tmp2, <8 x i16> %tmp8 ) ; <<8 x i16…
24 declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone
28 …%tmp9 = tail call <2 x i64> @llvm.x86.sse2.psrl.q( <2 x i64> %b1, <2 x i64> %c ) nounwind readnone…
32 declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) nounwind readnone
34 declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone
|
| D | vec_shift2.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep CPI
5 …%tmp2 = tail call <8 x i16> @llvm.x86.sse2.psrl.w( <8 x i16> %tmp1, <8 x i16> bitcast (<4 x i32> <…
12 …%tmp2 = tail call <4 x i32> @llvm.x86.sse2.psll.d( <4 x i32> %tmp1, <4 x i32> < i32 14, i32 undef,…
16 declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) nounwind readnone
17 declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) nounwind readnone
|
| D | avx-intrinsics-x86_64.ll | 5 %res = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
8 declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone
13 …%res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#u…
16 declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone
21 %res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
24 declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone
|
| D | maskmovdqu.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2,-avx | grep -i EDI
2 ; RUN: llc < %s -march=x86-64 -mattr=+sse2,-avx | grep -i RDI
9 tail call void @llvm.x86.sse2.maskmov.dqu( <16 x i8> %a, <16 x i8> %b, i8* %c )
13 declare void @llvm.x86.sse2.maskmov.dqu(<16 x i8>, <16 x i8>, i8*) nounwind
|
| D | illegal-vector-args-return.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=nehalem | grep "mulpd %xmm3, %xmm1"
2 ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=nehalem | grep "mulpd %xmm2, %xmm0"
3 ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=nehalem | grep "addps %xmm3, %xmm1"
4 ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=nehalem | grep "addps %xmm2, %xmm0"
|
| D | 2007-05-17-ShuffleISelBug.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
5 declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>)
7 declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>)
16 …%tmp838 = tail call <8 x i16> @llvm.x86.sse2.psrl.w( <8 x i16> %tmp832, <8 x i16> < i16 8, i16 und…
17 …%tmp1020 = tail call <16 x i8> @llvm.x86.sse2.packuswb.128( <8 x i16> zeroinitializer, <8 x i16> %…
|
| D | lfence.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep lfence
3 declare void @llvm.x86.sse2.lfence() nounwind
6 call void @llvm.x86.sse2.lfence()
|
| /external/libvpx/libvpx/vpx_dsp/x86/ |
| D | highbd_variance_sse2.c | 257 DECLS(sse2, sse);
279 unsigned int sse2; \
285 h, &sse2); \
287 sse += sse2; \
292 h, &sse2); \
294 sse += sse2; \
297 dst + 48, dst_stride, h, &sse2); \
299 sse += sse2; \
317 uint32_t sse2; \
323 h, &sse2); \
[all …]
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| D | vpx_asm_stubs.c | 62 FUN_CONV_1D(horiz, x_step_q4, filter_x, h, src, , sse2);
63 FUN_CONV_1D(vert, y_step_q4, filter_y, v, src - src_stride * 3, , sse2);
64 FUN_CONV_1D(avg_horiz, x_step_q4, filter_x, h, src, avg_, sse2);
65 FUN_CONV_1D(avg_vert, y_step_q4, filter_y, v, src - src_stride * 3, avg_, sse2);
77 FUN_CONV_2D(, sse2);
78 FUN_CONV_2D(avg_ , sse2);
143 HIGH_FUN_CONV_1D(horiz, x_step_q4, filter_x, h, src, , sse2);
144 HIGH_FUN_CONV_1D(vert, y_step_q4, filter_y, v, src - src_stride * 3, , sse2);
145 HIGH_FUN_CONV_1D(avg_horiz, x_step_q4, filter_x, h, src, avg_, sse2);
147 sse2);
[all …]
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| D | variance_sse2.c | 327 DECLS(sse2, sse);
345 unsigned int sse2; \
349 h, &sse2, NULL, NULL); \
351 sse += sse2; \
356 h, &sse2, NULL, NULL); \
358 sse += sse2; \
362 h, &sse2, NULL, NULL); \
364 sse += sse2; \
386 FNS(sse2, sse);
408 DECLS(sse2, sse);
[all …]
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| D | variance_avx2.c | 123 unsigned int sse2; in vpx_sub_pixel_variance64x64_avx2() local
127 64, &sse2); in vpx_sub_pixel_variance64x64_avx2()
129 *sse = sse1 + sse2; in vpx_sub_pixel_variance64x64_avx2()
158 unsigned int sse2; in vpx_sub_pixel_avg_variance64x64_avx2() local
162 sec + 32, 64, 64, &sse2); in vpx_sub_pixel_avg_variance64x64_avx2()
165 *sse = sse1 + sse2; in vpx_sub_pixel_avg_variance64x64_avx2()
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| /external/skia/gyp/ |
| D | libjpeg-turbo.gyp | 133 '../third_party/externals/libjpeg-turbo/simd/jccolor-sse2.asm',
135 '../third_party/externals/libjpeg-turbo/simd/jcgray-sse2.asm',
137 '../third_party/externals/libjpeg-turbo/simd/jcsample-sse2.asm',
139 '../third_party/externals/libjpeg-turbo/simd/jdcolor-sse2.asm',
141 '../third_party/externals/libjpeg-turbo/simd/jdmerge-sse2.asm',
143 '../third_party/externals/libjpeg-turbo/simd/jdsample-sse2.asm',
147 '../third_party/externals/libjpeg-turbo/simd/jfdctfst-sse2.asm',
149 '../third_party/externals/libjpeg-turbo/simd/jfdctint-sse2.asm',
151 '../third_party/externals/libjpeg-turbo/simd/jidctflt-sse2.asm',
154 '../third_party/externals/libjpeg-turbo/simd/jidctfst-sse2.asm',
[all …]
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| /external/clang/include/clang/Basic/ |
| D | BuiltinsX86.def | 159 TARGET_BUILTIN(__builtin_ia32_cvtpd2pi, "V2iV2d", "", "sse2")
160 TARGET_BUILTIN(__builtin_ia32_cvtpi2pd, "V2dV2i", "", "sse2")
161 TARGET_BUILTIN(__builtin_ia32_cvttpd2pi, "V2iV2d", "", "sse2")
162 TARGET_BUILTIN(__builtin_ia32_paddq, "V1LLiV1LLiV1LLi", "", "sse2")
163 TARGET_BUILTIN(__builtin_ia32_pmuludq, "V1LLiV2iV2i", "", "sse2")
164 TARGET_BUILTIN(__builtin_ia32_psubq, "V1LLiV1LLiV1LLi", "", "sse2")
198 TARGET_BUILTIN(__builtin_ia32_comisdeq, "iV2dV2d", "", "sse2")
199 TARGET_BUILTIN(__builtin_ia32_comisdlt, "iV2dV2d", "", "sse2")
200 TARGET_BUILTIN(__builtin_ia32_comisdle, "iV2dV2d", "", "sse2")
201 TARGET_BUILTIN(__builtin_ia32_comisdgt, "iV2dV2d", "", "sse2")
[all …]
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| /external/llvm/test/Transforms/InstCombine/ |
| D | x86-vector-shifts.ll | 11 %1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %v, i32 0)
19 %1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %v, i32 15)
27 %1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %v, i32 64)
34 %1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %v, i32 0)
42 %1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %v, i32 15)
50 %1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %v, i32 64)
107 %1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %v, i32 0)
115 %1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %v, i32 15)
122 %1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %v, i32 64)
129 %1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %v, i32 0)
[all …]
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| /external/valgrind/memcheck/tests/amd64/ |
| D | xor-undef-amd64.stdout.exp | 14 Complain sse2 pxor
16 No complain sse2 pxor
18 Complain sse2 xorpd
20 No complain sse2 xorpd
|
| /external/llvm/test/Instrumentation/MemorySanitizer/ |
| D | vector_shift.ll | 11 declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>)
12 declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32)
13 declare <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64>, i32)
14 declare <2 x i64> @llvm.x86.sse2.psll.dq.bs(<2 x i64>, i32)
40 %0 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %x, i32 %y)
48 ; CHECK: = call <8 x i16> @llvm.x86.sse2.pslli.w(
50 ; CHECK: call <8 x i16> @llvm.x86.sse2.pslli.w(
56 %0 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %x, <8 x i16> %y)
66 ; CHECK: = call <8 x i16> @llvm.x86.sse2.psrl.w(
68 ; CHECK: call <8 x i16> @llvm.x86.sse2.psrl.w(
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| D | vector_cvt.ll | 6 declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) nounwind readnone
7 declare <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double>, i32) nounwind readnone
14 %0 = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %value)
23 ; CHECK: call i32 @llvm.x86.sse2.cvtsd2si
32 %0 = tail call <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double> %vec, i32 %a)
45 ; CHECK: call <2 x double> @llvm.x86.sse2.cvtsi2sd
|