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Searched refs:sshl (Results 1 – 25 of 27) sorted by relevance

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/external/llvm/test/MC/AArch64/
Dneon-shift.s9 sshl v0.8b, v1.8b, v2.8b
10 sshl v0.16b, v1.16b, v2.16b
11 sshl v0.4h, v1.4h, v2.4h
12 sshl v0.8h, v1.8h, v2.8h
13 sshl v0.2s, v1.2s, v2.2s
14 sshl v0.4s, v1.4s, v2.4s
15 sshl v0.2d, v1.2d, v2.2d
Dneon-scalar-shift.s6 sshl d17, d31, d8
Dneon-diagnostics.s915 sshl v0.4s, v15.2s, v16.2s
971 sshl d0, d1, s2 define
Darm64-advsimd.s354 sshl.8b v0, v0, v0
425 ; CHECK: sshl.8b v0, v0, v0 ; encoding: [0x00,0x44,0x20,0x0e]
/external/libavc/common/armv8/
Dih264_iquant_itrans_recon_av8.s150 sshl v0.4s, v0.4s, v30.4s // q0 = q[i] = (p[i] << (qp/6)) where i = 0..3
151 sshl v2.4s, v2.4s, v30.4s // q1 = q[i] = (p[i] << (qp/6)) where i = 4..7
152 sshl v4.4s, v4.4s, v30.4s // q2 = q[i] = (p[i] << (qp/6)) where i = 8..11
153 sshl v6.4s, v6.4s, v30.4s // q3 = q[i] = (p[i] << (qp/6)) where i = 12..15
341 sshl v0.4s, v0.4s, v30.4s // q0 = q[i] = (p[i] << (qp/6)) where i = 0..3
342 sshl v2.4s, v2.4s, v30.4s // q1 = q[i] = (p[i] << (qp/6)) where i = 4..7
343 sshl v4.4s, v4.4s, v30.4s // q2 = q[i] = (p[i] << (qp/6)) where i = 8..11
344 sshl v6.4s, v6.4s, v30.4s // q3 = q[i] = (p[i] << (qp/6)) where i = 12..15
573 sshl v16.4s, v16.4s, v0.4s
574 sshl v17.4s, v17.4s, v0.4s
[all …]
Dih264_ihadamard_scaling_av8.s149 sshl v0.4s, v0.4s, v14.4s // q0 = q[i] = (p[i] << (qp/6)) where i = 0..3
150 sshl v1.4s, v1.4s, v14.4s // q1 = q[i] = (p[i] << (qp/6)) where i = 4..7
151 sshl v2.4s, v2.4s, v14.4s // q2 = q[i] = (p[i] << (qp/6)) where i = 8..11
152 sshl v3.4s, v3.4s, v14.4s // q3 = q[i] = (p[i] << (qp/6)) where i = 12..15
239 sshl v2.4s, v2.4s, v28.4s
240 sshl v3.4s, v3.4s, v28.4s
Dih264_resi_trans_quant_av8.s205 sshl v20.4s, v20.4s, v24.4s //shift row 1
206 sshl v21.4s, v21.4s, v24.4s //shift row 2
207 sshl v22.4s, v22.4s, v24.4s //shift row 3
208 sshl v23.4s, v23.4s, v24.4s //shift row 4
428 sshl v20.4s, v20.4s, v24.4s //shift row 1
429 sshl v21.4s, v21.4s, v24.4s //shift row 2
430 sshl v22.4s, v22.4s, v24.4s //shift row 3
431 sshl v23.4s, v23.4s, v24.4s //shift row 4
Dih264_iquant_itrans_recon_dc_av8.s140 sshl v0.4s, v0.4s, v30.4s
352 sshl v0.4s, v0.4s, v3.4s
/external/libhevc/common/arm64/
Dihevc_intra_pred_luma_planar.s209 sshl v27.8h, v27.8h, v29.8h //(1)shr
226 sshl v30.8h, v30.8h, v29.8h //(2)shr
243 sshl v28.8h, v28.8h, v29.8h //(3)shr
260 sshl v25.8h, v25.8h, v29.8h //(4)shr
276 sshl v16.8h, v16.8h, v29.8h //(5)shr
293 sshl v18.8h, v18.8h, v29.8h //(6)shr
309 sshl v26.8h, v26.8h, v29.8h //(7)shr
348 sshl v24.8h, v24.8h, v29.8h //(8)shr
382 sshl v27.8h, v27.8h, v29.8h //(1)shr
402 sshl v30.8h, v30.8h, v29.8h //(2)shr
[all …]
Dihevc_weighted_pred_uni.s183 sshl v4.4s,v4.4s,v28.4s
193 sshl v6.4s,v6.4s,v28.4s
199 sshl v7.4s,v7.4s,v28.4s
208 sshl v16.4s,v16.4s,v28.4s
Dihevc_intra_pred_chroma_planar.s213 sshl v12.8h, v12.8h, v14.8h //shr
217 sshl v28.8h, v28.8h, v14.8h
237 sshl v26.8h, v26.8h, v14.8h //shr
243 sshl v24.8h, v24.8h, v14.8h
263 sshl v22.8h, v22.8h, v14.8h //shr
278 sshl v20.8h, v20.8h, v14.8h
289 sshl v12.8h, v12.8h, v14.8h //shr
291 sshl v28.8h, v28.8h, v14.8h
Dihevc_weighted_pred_bi.s237 sshl v4.4s,v4.4s,v28.4s //vshlq_s32(i4_tmp1_t1, tmp_shift_t)
249 sshl v6.4s,v6.4s,v28.4s
259 sshl v19.4s,v19.4s,v28.4s
271 sshl v18.4s,v18.4s,v28.4s
Dihevc_intra_pred_luma_dc.s195 sshl d18, d6, d7 //(dc_val) shr by log2nt+1
448 sshl d18, d6, d7 //(dc_val) shr by log2nt+1
/external/llvm/test/CodeGen/AArch64/
Darm64-vshr.ll6 ; CHECK-NEXT: sshl.8h [[REG2:v[0-9]+]], [[REG2]], [[REG1]]
22 ; CHECK-NEXT: sshl.4s [[REG4:v[0-9]+]], [[REG4]], [[REG3]]
Darm64-vshift.ll1923 ; CHECK: sshl d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
/external/vixl/src/vixl/a64/
Dsimulator-a64.cc2642 case NEON_SSHL: sshl(vf, rd, rn, rm); break; in VisitNEON3Same()
2655 case NEON_SQSHL: sshl(vf, rd, rn, rm).SignedSaturate(vf); break; in VisitNEON3Same()
2657 case NEON_SRSHL: sshl(vf, rd, rn, rm).Round(vf); break; in VisitNEON3Same()
2662 sshl(vf, rd, rn, rm).Round(vf).SignedSaturate(vf); in VisitNEON3Same()
3520 case NEON_SSHL_scalar: sshl(vf, rd, rn, rm); break; in VisitNEONScalar3Same()
3539 sshl(vf, rd, rn, rm).SignedSaturate(vf); in VisitNEONScalar3Same()
3545 sshl(vf, rd, rn, rm).Round(vf); in VisitNEONScalar3Same()
3551 sshl(vf, rd, rn, rm).Round(vf).SignedSaturate(vf); in VisitNEONScalar3Same()
Dlogic-a64.cc1624 return sshl(vform, dst, extendedreg, shiftreg); in sshll()
1636 return sshl(vform, dst, extendedreg, shiftreg); in sshll2()
1704 return sshl(vform, dst, src, shiftreg).SignedSaturate(vform); in sqshl()
1726 return sshl(vform, dst, src, shiftreg).UnsignedSaturate(vform); in sqshlu()
1774 return sshl(vform, dst, src, shiftreg); in sshr()
1877 LogicVRegister Simulator::sshl(VectorFormat vform, in sshl() function in vixl::Simulator
Dsimulator-a64.h1720 LogicVRegister sshl(VectorFormat vform,
Dmacro-assembler-a64.h2191 V(sshl, Sshl) \
Dassembler-a64.h2549 void sshl(const VRegister& vd,
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt382 # CHECK: sshl v10.8b, v15.8b, v22.8b
384 # CHECK: sshl v10.4h, v15.4h, v22.4h
386 # CHECK: sshl v10.2s, v15.2s, v22.2s
388 # CHECK: sshl v0.2d, v1.2d, v2.2d
454 # CHECK: sshl d31, d31, d31
Darm64-advsimd.txt337 # CHECK: sshl.8b v0, v0, v0
/external/vixl/test/
Dtest-simulator-a64.cc3718 DEFINE_TEST_NEON_3SAME(sshl, Basic)
3795 DEFINE_TEST_NEON_3SAME_SCALAR_D(sshl, Basic)
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp28423 sshl d29, d28, d27 2ba96660fac6cea3d11abaa383dd738a ac03cf2c0fdfa87107730cbc71330e9b 6089e81262…
28425 sshl v29.2d, v28.2d, v27.2d ad051f081939ffa5f3e9bc24fa345ba4 73a6a07fabfe7ea865fb8564ec7909b7 e…
28426 sshl v29.4s, v28.4s, v27.4s f3dc275348d2f231f9dafb3cc9be7373 dcc8d058e31b0d31d1cc41ba594147b5 1…
28427 sshl v29.2s, v28.2s, v27.2s 38c5f134209a9cf3d5e472b114e001e9 b385173fe869fa3e3b63e4f2160bce5b c…
28428 sshl v29.8h, v28.8h, v27.8h 44f56394f5aaa1217e2ecdb712b356cc 6836ab23a2cd8655c928517a7c93a34e d…
28429 sshl v29.4h, v28.4h, v27.4h 1c00e1e98c5524f078ccf243080a17d2 ff70f17ad49ad7abfc2f6d45d0ad693f 6…
28430 sshl v29.16b, v28.16b, v27.16b c37acfa6aaf0499346d2c34838b9e7ad 7bc74db7422511735b8c1c48552ec4e5…
28431 sshl v29.8b, v28.8b, v27.8b 3ef7913f11ce35406d5425b9e8956a11 e0d0234fb0c156e3685341754eea59f2 f…
/external/vixl/doc/
Dsupported-instructions.md3692 void sshl(const VRegister& vd,

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