| /external/libvpx/libvpx/vp8/common/arm/armv6/ |
| D | iwalsh_v6.asm | 75 sxth r2, r2
76 sxth r3, r3
86 sxth r4, r4
87 sxth r5, r5
112 sxth r6, r6
113 sxth r7, r7
123 sxth r8, r8
124 sxth r9, r9
|
| /external/llvm/test/CodeGen/ARM/ |
| D | fast-isel-icmp.ll | 8 ; ARM: sxth r0, r0
9 ; ARM: sxth r1, r1
12 ; THUMB: sxth r0, r0
13 ; THUMB: sxth r1, r1
|
| D | fast-isel.ll | 106 ; THUMB: sxth
110 ; ARM: sxth
126 ; THUMB: sxth
132 ; ARM: sxth
|
| D | returned-ext.ll | 70 ; CHECKELF: sxth r0, {{r[0-9]+}}
76 ; CHECKT2D: sxth r0, {{r[0-9]+}}
164 ; CHECKELF: sxth r0, [[SAVEX]]
171 ; CHECKT2D: sxth r0, [[SAVEX]]
|
| D | fast-isel-ret.ll | 38 ; CHECK: sxth r0, r0
55 ; CHECK-NOT: sxth
|
| D | fast-isel-fold.ll | 66 ; ARM-NOT: sxth
69 ; THUMB-NOT: sxth
|
| D | fast-isel-conversion.ll | 24 ; ARM: sxth r0, r0
28 ; THUMB: sxth r0, r0
70 ; ARM: sxth r0, r0
74 ; THUMB: sxth r0, r0
|
| D | divmod-eabi.ll | 38 ; EABI: sxth r0, r0
40 ; GNU: sxth r0, r0
42 ; DARWIN: sxth r0, r0
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-arithmetic-encoding.s | 175 add w1, w2, w3, sxth
184 ; CHECK: add w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x0b]
192 add x1, x2, w3, sxth
199 ; CHECK: add x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x8b]
219 sub w1, w2, w3, sxth
228 ; CHECK: sub w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x4b]
236 sub x1, x2, w3, sxth
243 ; CHECK: sub x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0xcb]
263 adds w1, w2, w3, sxth
272 ; CHECK: adds w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x2b]
[all …]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | addsub_ext.ll | 178 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth
183 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth #1
189 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth
194 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth #4
206 ; CHECK: cmp {{x[0-9]+}}, {{w[0-9]+}}, sxth
253 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth
258 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth #1
264 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth
269 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth #4
|
| D | fast-isel-int-ext2.ll | 95 ; CHECK-NOT: sxth
123 ; CHECK-NOT: sxth
236 ; CHECK-NOT: sxth
264 ; CHECK-NOT: sxth
383 ; CHECK-NOT: sxth
413 ; CHECK-NOT: sxth
|
| D | adc.ll | 58 ; CHECK-LE: adds x0, x0, w2, sxth #3
60 ; CHECK-BE: adds x1, x1, w2, sxth #3
|
| D | fast-isel-int-ext.ll | 219 ; CHECK-NOT: sxth
241 ; CHECK-NOT: sxth
330 ; CHECK-NOT: sxth
352 ; CHECK-NOT: sxth
447 ; CHECK-NOT: sxth
471 ; CHECK-NOT: sxth
|
| D | fast-isel-int-ext3.ll | 77 ; CHECK: sxth w0, [[REG]]
99 ; CHECK: sxth x0, [[REG]]
|
| D | arm64-narrow-ldst-merge.ll | 67 ; CHECK-DAG: sxth [[HI_PART:w[0-9]+]], [[NEW_DEST]]
86 ; BE-DAG: sxth [[LO_PART:w[0-9]+]], [[NEW_DEST]]
103 ; LE-DAG: sxth [[LO_PART:w[0-9]+]], [[NEW_DEST]]
195 ; CHECK-DAG: sxth [[HI_PART:w[0-9]+]], [[NEW_DEST]]
212 ; LE-DAG: sxth [[HI_PART:w[0-9]+]], [[NEW_DEST]]
233 ; BE-DAG: sxth [[HI_PART:w[0-9]+]], [[NEW_DEST]]
|
| D | bitfield.ll | 43 ; CHECK: sxth {{w[0-9]+}}, {{w[0-9]+}}
59 ; CHECK: sxth {{x[0-9]+}}, {{w[0-9]+}}
149 ; CHECK: sxth {{x[0-9]+}}, {{w[0-9]+}}
|
| D | arm64-fast-isel-icmp.ll | 156 ; CHECK: sxth w0, w0
157 ; CHECK: cmp w0, w1, sxth
210 ; CHECK: sxth w0, w0
|
| D | arm64-arith.ll | 105 ; CHECK: add w0, w1, w0, sxth
115 ; CHECK: add w0, w1, w0, sxth #2
159 ; CHECK: sxth [[REG:x[0-9]+]], w0
|
| /external/llvm/test/MC/ARM/ |
| D | thumb.s | 26 sxth r2, r3
28 @ CHECK: sxth r2, r3 @ encoding: [0x1a,0xb2]
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-arithmetic.txt | 178 # CHECK: add w1, w2, w3, sxth
193 # CHECK: add x1, x2, w3, sxth
220 # CHECK: sub w1, w2, w3, sxth
235 # CHECK: sub x1, x2, w3, sxth
262 # CHECK: adds w1, w2, w3, sxth
277 # CHECK: adds x1, x2, w3, sxth
300 # CHECK: subs w1, w2, w3, sxth
315 # CHECK: subs x1, x2, w3, sxth
|
| /external/llvm/test/MC/Disassembler/Hexagon/ |
| D | alu32_pred.txt | 116 # CHECK: if (p3) r17 = sxth(r21)
118 # CHECK: if (!p3) r17 = sxth(r21)
121 # CHECK-NEXT: if (p3.new) r17 = sxth(r21)
124 # CHECK-NEXT: if (!p3.new) r17 = sxth(r21)
|
| /external/llvm/test/CodeGen/Hexagon/intrinsics/ |
| D | alu32_alu.ll | 88 declare i32 @llvm.hexagon.A2.sxth(i32)
90 %z = call i32 @llvm.hexagon.A2.sxth(i32 %a)
93 ; CHECK: = sxth({{.*}})
|
| /external/llvm/lib/CodeGen/ |
| D | README.txt | 8 sxth r3, r3
18 sxth r3, r3
26 sxth r3, r3
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | thumb2-sxt-uxt.ll | 5 ; CHECK: sxth
|
| /external/llvm/test/CodeGen/Hexagon/ |
| D | maxh.ll | 4 ; CHECK-NOT: sxth
|