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Searched refs:uaddlv (Results 1 – 17 of 17) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-across.s21 uaddlv h0, v1.8b
22 uaddlv h0, v1.16b
23 uaddlv s0, v1.4h
24 uaddlv s0, v1.8h
25 uaddlv d0, v1.4s define
Dneon-diagnostics.s3743 uaddlv b0, v1.8b
3744 uaddlv b0, v1.16b
3745 uaddlv h0, v1.4h
3746 uaddlv h0, v1.8h
3747 uaddlv s0, v1.2s
3748 uaddlv s0, v1.4s
3749 uaddlv d0, v1.2s define
/external/llvm/test/CodeGen/AArch64/
Darm64-simd-scalar-to-vector.ll5 ; CHECK: uaddlv.16b h0, v0
10 ; CHECK-FAST: uaddlv.16b
13 %tmp = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v16i8(<16 x i8> %a) nounwind
22 declare i32 @llvm.aarch64.neon.uaddlv.i32.v16i8(<16 x i8>) nounwind readnone
Darm64-neon-across.ll61 declare i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32>)
63 declare i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16>)
65 declare i32 @llvm.aarch64.neon.uaddlv.i32.v16i8(<16 x i8>)
73 declare i32 @llvm.aarch64.neon.uaddlv.i32.v4i16(<4 x i16>)
75 declare i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8>)
100 ; CHECK: uaddlv h{{[0-9]+}}, {{v[0-9]+}}.8b
102 %uaddlvv.i = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8> %a)
109 ; CHECK: uaddlv s{{[0-9]+}}, {{v[0-9]+}}.4h
111 %uaddlvv.i = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v4i16(<4 x i16> %a)
142 ; CHECK: uaddlv h{{[0-9]+}}, {{v[0-9]+}}.16b
[all …]
Darm64-popcnt.ll10 ; CHECK: uaddlv.8b h0, v0
28 ; CHECK: uaddlv.8b h0, v0
44 ; CHECK: uaddlv.8b h0, v0
Darm64-vaddlv.ll19 %vaddlv.i = tail call i64 @llvm.aarch64.neon.uaddlv.i64.v2i32(<2 x i32> %a1) nounwind
23 declare i64 @llvm.aarch64.neon.uaddlv.i64.v2i32(<2 x i32>) nounwind readnone
/external/vixl/src/vixl/a64/
Dsimulator-a64.h1760 LogicVRegister uaddlv(VectorFormat vform,
Dmacro-assembler-a64.h2312 V(uaddlv, Uaddlv) \
Dassembler-a64.h3015 void uaddlv(const VRegister& vd,
Dsimulator-a64.cc2785 case NEON_UADDLV: uaddlv(vf, rd, rn); break; in VisitNEONAcrossLanes()
Dlogic-a64.cc1437 LogicVRegister Simulator::uaddlv(VectorFormat vform, in uaddlv() function in vixl::Simulator
Dassembler-a64.cc4040 void Assembler::uaddlv(const VRegister& vd, in uaddlv() function in vixl::Assembler
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp27417 uaddlv h3, v19.16b 32c3a575a3a60df92a502ab22dc4922c 12548825f7c9ded60ac49ce1fcc16275 0000000000…
27418 uaddlv h3, v19.8b 12d337600a277794b514da44733fdf4d 87cad64dc73cf347a83efe59576fff85 00000000000…
27419 uaddlv s3, v19.8h 2d6ffe15b726901bf02813c432bcef3e d0c53178f4a60f5c8d02bff74498b61d 00000000000…
27420 uaddlv s3, v19.4h e47858740985b76e3a6e3411ca1d21df 4d24f884dfe791f51aef429b211ce81d 00000000000…
27421 uaddlv d3, v19.4s 96cfa85d61224d6cf3c49d0d9c40d510 5dc88b53e7dfd9f1aee4e42550dbf465 00000000000…
/external/vixl/test/
Dtest-simulator-a64.cc4042 DEFINE_TEST_NEON_ACROSS_LONG(uaddlv, Basic)
/external/vixl/doc/
Dsupported-instructions.md4124 void uaddlv(const VRegister& vd,
/external/valgrind/
DNEWS816 335736 arm64: unhandled instruction: uaddlv
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td4022 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;