/external/llvm/test/CodeGen/AArch64/ |
D | fp16-v16-instructions.ll | 57 ; CHECK-DAG: ucvtf [[S0:v[0-9]+\.4s]], v0.4s 58 ; CHECK-DAG: ucvtf [[S1:v[0-9]+\.4s]], v1.4s 59 ; CHECK-DAG: ucvtf [[S2:v[0-9]+\.4s]], v2.4s 60 ; CHECK-DAG: ucvtf [[S3:v[0-9]+\.4s]], v3.4s 75 ; CHECK-DAG: ucvtf [[D0:v[0-9]+\.2d]], v0.2d 76 ; CHECK-DAG: ucvtf [[D1:v[0-9]+\.2d]], v1.2d 77 ; CHECK-DAG: ucvtf [[D2:v[0-9]+\.2d]], v2.2d 78 ; CHECK-DAG: ucvtf [[D3:v[0-9]+\.2d]], v3.2d 79 ; CHECK-DAG: ucvtf [[D4:v[0-9]+\.2d]], v4.2d 80 ; CHECK-DAG: ucvtf [[D5:v[0-9]+\.2d]], v5.2d [all …]
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D | complex-int-to-fp.ll | 25 ; CHECK-NEXT: ucvtf.2d v0, [[VAL64]] 46 ; CHECK: ucvtf.2d v0, [[VAL64]] 67 ; CHECK: ucvtf.2d v0, [[VAL64]] 83 ; CHECK: ucvtf.2d [[VAL64:v[0-9]+]], v0 103 ; CHECK: ucvtf.2s v0, [[VAL32]] 122 ; CHECK: ucvtf.2s v0, [[VAL32]] 140 ; CHECK: ucvtf.4s v0, [[VAL32]] 160 ; CHECK: ucvtf.4s v0, [[VAL32]]
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D | fcvt-fixed.ll | 156 ; CHECK: ucvtf {{s[0-9]+}}, {{w[0-9]+}}, #7 161 ; CHECK: ucvtf {{s[0-9]+}}, {{w[0-9]+}}, #32 166 ; CHECK: ucvtf {{s[0-9]+}}, {{x[0-9]+}}, #7 171 ; CHECK: ucvtf {{s[0-9]+}}, {{x[0-9]+}}, #64 176 ; CHECK: ucvtf {{d[0-9]+}}, {{w[0-9]+}}, #7 181 ; CHECK: ucvtf {{d[0-9]+}}, {{w[0-9]+}}, #32 186 ; CHECK: ucvtf {{d[0-9]+}}, {{x[0-9]+}}, #7 191 ; CHECK: ucvtf {{d[0-9]+}}, {{x[0-9]+}}, #64
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D | arm64-scvt.ll | 19 ; CHECK: ucvtf s0, s0 39 ; CHECK: ucvtf d0, d0 75 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] 88 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] 101 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] 115 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]] 129 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] 142 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] 155 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] 169 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]] [all …]
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D | fcvt-int.ll | 68 ; CHECK-DAG: ucvtf [[UNSIG:s[0-9]+]], {{w[0-9]+}} 82 ; CHECK-DAG: ucvtf [[UNSIG:d[0-9]+]], {{w[0-9]+}} 96 ; CHECK-DAG: ucvtf [[UNSIG:s[0-9]+]], {{x[0-9]+}} 110 ; CHECK-DAG: ucvtf [[UNSIG:d[0-9]+]], {{x[0-9]+}}
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D | fdiv_combine.ll | 16 ; CHECK: ucvtf.2s v0, v0, #3 76 ; CHECK: ucvtf.4s v0, v0, #1 97 ; CHECK: ucvtf.2d v0, v0 109 ; CHECK: ucvtf.2d v0, v0, #1
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D | arm64-vcvt_n.ll | 5 ; CHECK: ucvtf.2s v0, v0, #9 21 ; CHECK: ucvtf.4s v0, v0, #18
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D | fp16-v8-instructions.ll | 314 ; CHECK-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]] 315 ; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]] 328 ; CHECK-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]] 329 ; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]] 340 ; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s 341 ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.4s]], v1.4s 352 ; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d 353 ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
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D | arm64-convert-v4f64.ll | 36 ; CHECK-DAG: ucvtf v[[LHS:[0-9]+]].2d, v0.2d 37 ; CHECK-DAG: ucvtf v[[RHS:[0-9]+]].2d, v1.2d
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D | arm64-vcvt_f32_su32.ll | 5 ; CHECK: ucvtf.2s v0, v0 22 ; CHECK: ucvtf.4s v0, v0
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D | arm64-extend-int-to-fp.ll | 6 ; CHECK-NEXT: ucvtf.4s v0, v0
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D | arm64-fast-isel-conversion.ll | 306 ; CHECK: ucvtf s0, w0 331 ; CHECK: ucvtf s0, w0 340 ; CHECK: ucvtf s0, x0 349 ; CHECK: ucvtf d0, w0 358 ; CHECK: ucvtf d0, x0
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D | fpconv-vector-op-scalarize.ll | 21 ; CHECK-NEXT: ucvtf d0, [[GPR]]
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D | fp16-v4-instructions.ll | 181 ; CHECK-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]] 192 ; CHECK-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]] 202 ; CHECK-NEXT: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s 211 ; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d 212 ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
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D | arm64-fast-isel-noconvert.ll | 7 ; CHECK: ucvtf.4s v0, v0
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/external/llvm/test/MC/AArch64/ |
D | neon-scalar-cvt.s | 21 ucvtf h20, h12 22 ucvtf s22, s13 23 ucvtf d21, d14 45 ucvtf h22, h13, #16 46 ucvtf s22, s13, #32 47 ucvtf d21, d14, #64
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D | arm64-fp-encoding.s | 500 ucvtf h1, w2 501 ucvtf h1, w2, #1 502 ucvtf s1, w2 503 ucvtf s1, w2, #1 504 ucvtf d1, w2 define 505 ucvtf d1, w2, #1 define 506 ucvtf h1, x2 507 ucvtf h1, x2, #1 508 ucvtf s1, x2 509 ucvtf s1, x2, #1 [all …]
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D | neon-simd-shift.s | 408 ucvtf v0.4h, v1.4h, #3 409 ucvtf v0.8h, v1.8h, #3 410 ucvtf v0.2s, v1.2s, #3 411 ucvtf v0.4s, v1.4s, #3 412 ucvtf v0.2d, v1.2d, #3
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D | neon-simd-misc.s | 694 ucvtf v4.4h, v0.4h 695 ucvtf v6.8h, v8.8h 696 ucvtf v6.4s, v8.4s 697 ucvtf v6.2d, v8.2d 698 ucvtf v4.2s, v0.2s
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D | basic-a64-instructions.s | 2037 ucvtf s23, w19, #1 2038 ucvtf s31, wzr, #20 2039 ucvtf s14, w0, #32 2044 ucvtf s23, x19, #1 2045 ucvtf s31, xzr, #20 2046 ucvtf s14, x0, #64 2051 ucvtf d23, w19, #1 2052 ucvtf d31, wzr, #20 2053 ucvtf d14, w0, #32 2058 ucvtf d23, x19, #1 [all …]
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D | basic-a64-diagnostics.s | 1747 ucvtf w13, s31, #0 1748 ucvtf w19, s20, #33 1749 ucvtf wsp, s19, #14 1760 ucvtf x13, s31, #0 1761 ucvtf x19, s20, #65 1762 ucvtf sp, s19, #14
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D | neon-diagnostics.s | 2042 ucvtf v0.2s, v1.2s, #33 2043 ucvtf v0.4s, v1.4s, #33 2044 ucvtf v0.2d, v1.2d, #65 5225 ucvtf s22, s13, #34 5226 ucvtf d21, d14, #65 5227 ucvtf d21, s14, #64 5958 ucvtf v0.16b, v31.16b 5959 ucvtf v2.8h, v4.8h 5960 ucvtf v1.8b, v9.8b 5961 ucvtf v13.4h, v21.4h
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D | arm64-advsimd.s | 602 ucvtf.2s v0, v0 652 ; CHECK: ucvtf.2s v0, v0 ; encoding: [0x00,0xd8,0x21,0x2e] 1378 ucvtf s0, s0, #1 1379 ucvtf d0, d0, #2 define 1427 ; CHECK: ucvtf s0, s0, #1 ; encoding: [0x00,0xe4,0x3f,0x7f] 1428 ; CHECK: ucvtf d0, d0, #2 ; encoding: [0x00,0xe4,0x7e,0x7f] 1566 ucvtf.2s v0, v0, #1 1567 ucvtf.4s v0, v0, #2 1568 ucvtf.2d v0, v0, #3 1738 ; CHECK: ucvtf.2s v0, v0, #1 ; encoding: [0x00,0xe4,0x3f,0x2f] [all …]
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/external/v8/test/cctest/ |
D | test-disasm-arm64.cc | 1537 COMPARE(ucvtf(d28, w29), "ucvtf d28, w29"); in TEST_() 1538 COMPARE(ucvtf(s28, w29), "ucvtf s28, w29"); in TEST_() 1539 COMPARE(ucvtf(d0, x1), "ucvtf d0, x1"); in TEST_() 1540 COMPARE(ucvtf(s0, x1), "ucvtf s0, x1"); in TEST_() 1541 COMPARE(ucvtf(d0, x1, 0), "ucvtf d0, x1"); in TEST_() 1542 COMPARE(ucvtf(s0, x1, 0), "ucvtf s0, x1"); in TEST_() 1549 COMPARE(ucvtf(d7, x8, 2), "ucvtf d7, x8, #2"); in TEST_() 1550 COMPARE(ucvtf(s7, x8, 2), "ucvtf s7, x8, #2"); in TEST_() 1551 COMPARE(ucvtf(d9, x10, 16), "ucvtf d9, x10, #16"); in TEST_() 1552 COMPARE(ucvtf(s9, x10, 16), "ucvtf s9, x10, #16"); in TEST_() [all …]
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | basic-a64-instructions.txt | 1646 # FP16: ucvtf h23, w19, #1 1647 # FP16: ucvtf h31, wzr, #20 1648 # FP16: ucvtf h14, w0, #32 1653 # FP16: ucvtf h23, x19, #1 1654 # FP16: ucvtf h31, xzr, #20 1655 # FP16: ucvtf h14, x0, #64 1660 # CHECK: ucvtf s23, w19, #1 1661 # CHECK: ucvtf s31, wzr, #20 1662 # CHECK: ucvtf s14, w0, #32 1667 # CHECK: ucvtf s23, x19, #1 [all …]
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