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/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_eu_emit.c517 insn->bits3.urb_gen7.opcode = 0; /* URB_WRITE_HWORD */ in brw_set_urb_message()
518 insn->bits3.urb_gen7.offset = offset; in brw_set_urb_message()
520 insn->bits3.urb_gen7.swizzle_control = swizzle_control; in brw_set_urb_message()
522 insn->bits3.urb_gen7.per_slot_offset = 0; in brw_set_urb_message()
523 insn->bits3.urb_gen7.complete = complete; in brw_set_urb_message()
Dbrw_structs.h1383 } urb_gen7; member