D | logic-a64.cc | 1663 LogicVRegister extendedreg = uxtl(vform, temp2, src); in ushll() 2441 LogicVRegister Simulator::uxtl(VectorFormat vform, in uxtl() function in vixl::Simulator 2790 uxtl(vform, temp1, src1); in uaddl() 2791 uxtl(vform, temp2, src2); in uaddl() 2814 uxtl(vform, temp, src2); in uaddw() 2882 uxtl(vform, temp1, src1); in usubl() 2883 uxtl(vform, temp2, src2); in usubl() 2906 uxtl(vform, temp, src2); in usubw() 2974 uxtl(vform, temp1, src1); in uabal() 2975 uxtl(vform, temp2, src2); in uabal() [all …]
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