Home
last modified time | relevance | path

Searched refs:val2 (Results 1 – 25 of 317) sorted by relevance

12345678910>>...13

/external/ceres-solver/internal/ceres/miniglog/glog/
Dlogging.h359 #define CHECK_OP(val1, val2, op) LOG_IF_FALSE(FATAL, ((val1) op (val2))) \ argument
360 << "Check failed: " #val1 " " #op " " #val2 " "
363 #define CHECK_EQ(val1, val2) CHECK_OP(val1, val2, ==) argument
364 #define CHECK_NE(val1, val2) CHECK_OP(val1, val2, !=) argument
365 #define CHECK_LE(val1, val2) CHECK_OP(val1, val2, <=) argument
366 #define CHECK_LT(val1, val2) CHECK_OP(val1, val2, <) argument
367 #define CHECK_GE(val1, val2) CHECK_OP(val1, val2, >=) argument
368 #define CHECK_GT(val1, val2) CHECK_OP(val1, val2, >) argument
372 # define DCHECK_EQ(val1, val2) CHECK_OP(val1, val2, ==) argument
373 # define DCHECK_NE(val1, val2) CHECK_OP(val1, val2, !=) argument
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dvec-move-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 ret <16 x i8> %val2
14 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
18 ret <8 x i16> %val2
22 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
26 ret <4 x i32> %val2
30 define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
34 ret <2 x i64> %val2
38 define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) {
42 ret <4 x float> %val2
[all …]
Dvec-min-04.ll6 define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp slt <2 x i64> %val2, %val1
11 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
16 define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) {
20 %cmp = icmp sle <2 x i64> %val2, %val1
21 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
26 define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) {
30 %cmp = icmp sgt <2 x i64> %val2, %val1
31 %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
36 define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
[all …]
Dvec-max-02.ll6 define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp slt <8 x i16> %val1, %val2
11 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
16 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
20 %cmp = icmp sle <8 x i16> %val1, %val2
21 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
26 define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) {
30 %cmp = icmp sgt <8 x i16> %val1, %val2
31 %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
36 define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2) {
[all …]
Dvec-max-04.ll6 define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp slt <2 x i64> %val1, %val2
11 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
16 define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) {
20 %cmp = icmp sle <2 x i64> %val1, %val2
21 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
26 define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) {
30 %cmp = icmp sgt <2 x i64> %val1, %val2
31 %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
36 define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
[all …]
Dvec-min-03.ll6 define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) {
10 %cmp = icmp slt <4 x i32> %val2, %val1
11 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
16 define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) {
20 %cmp = icmp sle <4 x i32> %val2, %val1
21 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
26 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
30 %cmp = icmp sgt <4 x i32> %val2, %val1
31 %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
36 define <4 x i32> @f4(<4 x i32> %val1, <4 x i32> %val2) {
[all …]
Dvec-min-02.ll6 define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp slt <8 x i16> %val2, %val1
11 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
16 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
20 %cmp = icmp sle <8 x i16> %val2, %val1
21 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
26 define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) {
30 %cmp = icmp sgt <8 x i16> %val2, %val1
31 %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
36 define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2) {
[all …]
Dvec-max-03.ll6 define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) {
10 %cmp = icmp slt <4 x i32> %val1, %val2
11 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
16 define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) {
20 %cmp = icmp sle <4 x i32> %val1, %val2
21 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
26 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
30 %cmp = icmp sgt <4 x i32> %val1, %val2
31 %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
36 define <4 x i32> @f4(<4 x i32> %val1, <4 x i32> %val2) {
[all …]
Dvec-min-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp slt <16 x i8> %val2, %val1
11 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
16 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
20 %cmp = icmp sle <16 x i8> %val2, %val1
21 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
26 define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
30 %cmp = icmp sgt <16 x i8> %val2, %val1
31 %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
36 define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
[all …]
Dvec-max-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp slt <16 x i8> %val1, %val2
11 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
16 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
20 %cmp = icmp sle <16 x i8> %val1, %val2
21 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
26 define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
30 %cmp = icmp sgt <16 x i8> %val1, %val2
31 %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
36 define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
[all …]
Dvec-cmp-03.ll6 define <4 x i32> @f1(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
10 %cmp = icmp eq <4 x i32> %val1, %val2
16 define <4 x i32> @f2(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
21 %cmp = icmp ne <4 x i32> %val1, %val2
27 define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
31 %cmp = icmp sgt <4 x i32> %val1, %val2
37 define <4 x i32> @f4(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
42 %cmp = icmp sge <4 x i32> %val1, %val2
48 define <4 x i32> @f5(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
53 %cmp = icmp sle <4 x i32> %val1, %val2
[all …]
Dvec-cmp-02.ll6 define <8 x i16> @f1(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp eq <8 x i16> %val1, %val2
16 define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
21 %cmp = icmp ne <8 x i16> %val1, %val2
27 define <8 x i16> @f3(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
31 %cmp = icmp sgt <8 x i16> %val1, %val2
37 define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
42 %cmp = icmp sge <8 x i16> %val1, %val2
48 define <8 x i16> @f5(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
53 %cmp = icmp sle <8 x i16> %val1, %val2
[all …]
Dvec-cmp-01.ll6 define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp eq <16 x i8> %val1, %val2
16 define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
21 %cmp = icmp ne <16 x i8> %val1, %val2
27 define <16 x i8> @f3(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
31 %cmp = icmp sgt <16 x i8> %val1, %val2
37 define <16 x i8> @f4(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
42 %cmp = icmp sge <16 x i8> %val1, %val2
48 define <16 x i8> @f5(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
53 %cmp = icmp sle <16 x i8> %val1, %val2
[all …]
Dvec-cmp-04.ll6 define <2 x i64> @f1(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp eq <2 x i64> %val1, %val2
16 define <2 x i64> @f2(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
21 %cmp = icmp ne <2 x i64> %val1, %val2
27 define <2 x i64> @f3(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
31 %cmp = icmp sgt <2 x i64> %val1, %val2
37 define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
42 %cmp = icmp sge <2 x i64> %val1, %val2
48 define <2 x i64> @f5(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
53 %cmp = icmp sle <2 x i64> %val1, %val2
[all …]
Dvec-cmp-06.ll6 define <2 x i64> @f1(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
10 %cmp = fcmp oeq <2 x double> %val1, %val2
16 define <2 x i64> @f2(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
22 %cmp = fcmp one <2 x double> %val1, %val2
28 define <2 x i64> @f3(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
32 %cmp = fcmp ogt <2 x double> %val1, %val2
38 define <2 x i64> @f4(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
42 %cmp = fcmp oge <2 x double> %val1, %val2
48 define <2 x i64> @f5(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
52 %cmp = fcmp ole <2 x double> %val1, %val2
[all …]
Dvec-perm-08.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
19 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
23 %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
32 define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
36 %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
45 define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
49 %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
71 define <8 x i16> @f6(<8 x i16> %val1, <8 x i16> %val2) {
75 %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
[all …]
Dvec-sub-01.ll6 define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
10 %ret = sub <16 x i8> %val1, %val2
15 define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
19 %ret = sub <8 x i16> %val1, %val2
24 define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
28 %ret = sub <4 x i32> %val1, %val2
33 define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
37 %ret = sub <2 x i64> %val1, %val2
45 define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) {
64 %ret = fsub <4 x float> %val1, %val2
[all …]
/external/valgrind/none/tests/s390x/
Dclgrj.c31 register uint64_t val2 asm("r8") = value2; in compare_never()
40 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_never()
47 register uint64_t val2 asm("r8") = value2; in compare_always()
56 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_always()
63 register uint64_t val2 asm("r8") = value2; in compare_le()
72 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_le()
79 register uint64_t val2 asm("r8") = value2; in compare_ge()
88 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_ge()
95 register uint64_t val2 asm("r8") = value2; in compare_gt()
104 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_gt()
[all …]
Dclrj.c31 register uint32_t val2 asm("r8") = value2; in compare_never()
40 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_never()
47 register uint32_t val2 asm("r8") = value2; in compare_always()
56 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_always()
63 register uint32_t val2 asm("r8") = value2; in compare_le()
72 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_le()
79 register uint32_t val2 asm("r8") = value2; in compare_ge()
88 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_ge()
95 register uint32_t val2 asm("r8") = value2; in compare_gt()
104 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_gt()
[all …]
Dcgrj.c31 register int64_t val2 asm("r8") = value2; in compare_never()
40 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_never()
47 register int64_t val2 asm("r8") = value2; in compare_always()
56 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_always()
63 register int64_t val2 asm("r8") = value2; in compare_le()
72 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_le()
79 register int64_t val2 asm("r8") = value2; in compare_ge()
88 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_ge()
95 register int64_t val2 asm("r8") = value2; in compare_gt()
104 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_gt()
[all …]
Dcrj.c31 register int32_t val2 asm("r8") = value2; in compare_never()
40 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_never()
47 register int32_t val2 asm("r8") = value2; in compare_always()
56 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_always()
63 register int32_t val2 asm("r8") = value2; in compare_le()
72 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_le()
79 register int32_t val2 asm("r8") = value2; in compare_ge()
88 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_ge()
95 register int32_t val2 asm("r8") = value2; in compare_gt()
104 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_gt()
[all …]
/external/libbrillo/brillo/
Dany_unittest.cc19 Any val2 = val; in TEST() local
21 EXPECT_TRUE(val2.IsEmpty()); in TEST()
34 Any val2(3.1415926); in TEST() local
35 EXPECT_FALSE(val2.IsEmpty()); in TEST()
36 EXPECT_TRUE(val2.IsTypeCompatible<double>()); in TEST()
37 EXPECT_FALSE(val2.IsTypeCompatible<int>()); in TEST()
38 EXPECT_DOUBLE_EQ(3.1415926, val2.Get<double>()); in TEST()
66 Any val2; in TEST() local
67 EXPECT_TRUE(val2.IsEmpty()); in TEST()
68 val2 = val; in TEST()
[all …]
/external/libweave/third_party/chromium/base/
Dlogging.h403 #define CHECK_OP(name, op, val1, val2) CHECK((val1) op (val2)) argument
418 #define CHECK_OP(name, op, val1, val2) \ argument
421 logging::Check##name##Impl((val1), (val2), \
422 #val1 " " #op " " #val2)) \
481 #define CHECK_EQ(val1, val2) CHECK_OP(EQ, ==, val1, val2) argument
482 #define CHECK_NE(val1, val2) CHECK_OP(NE, !=, val1, val2) argument
483 #define CHECK_LE(val1, val2) CHECK_OP(LE, <=, val1, val2) argument
484 #define CHECK_LT(val1, val2) CHECK_OP(LT, < , val1, val2) argument
485 #define CHECK_GE(val1, val2) CHECK_OP(GE, >=, val1, val2) argument
486 #define CHECK_GT(val1, val2) CHECK_OP(GT, > , val1, val2) argument
[all …]
/external/regex-re2/util/
Dlogging.h15 #define DCHECK_EQ(val1, val2) assert((val1) == (val2)) argument
16 #define DCHECK_NE(val1, val2) assert((val1) != (val2)) argument
17 #define DCHECK_LE(val1, val2) assert((val1) <= (val2)) argument
18 #define DCHECK_LT(val1, val2) assert((val1) < (val2)) argument
19 #define DCHECK_GE(val1, val2) assert((val1) >= (val2)) argument
20 #define DCHECK_GT(val1, val2) assert((val1) > (val2)) argument
/external/llvm/test/CodeGen/NVPTX/
Dmulwide.ll11 %val2 = mul i32 %val0, %val1
12 ret i32 %val2
22 %val2 = mul i32 %val0, %val1
23 ret i32 %val2
33 %val2 = mul i32 %val0, %val1
34 ret i32 %val2
44 %val2 = mul i32 %val0, %val1
45 ret i32 %val2
55 %val2 = mul i64 %val0, %val1
56 ret i64 %val2
[all …]

12345678910>>...13