Searched refs:virtReg (Results 1 – 4 of 4) sorted by relevance
92 bool hasPhys(unsigned virtReg) const { in hasPhys() argument93 return getPhys(virtReg) != NO_PHYS_REG; in hasPhys()98 unsigned getPhys(unsigned virtReg) const { in getPhys() argument99 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); in getPhys()100 return Virt2PhysMap[virtReg]; in getPhys()105 void assignVirt2Phys(unsigned virtReg, unsigned physReg) { in assignVirt2Phys() argument106 assert(TargetRegisterInfo::isVirtualRegister(virtReg) && in assignVirt2Phys()108 assert(Virt2PhysMap[virtReg] == NO_PHYS_REG && in assignVirt2Phys()111 Virt2PhysMap[virtReg] = physReg; in assignVirt2Phys()116 void clearVirt(unsigned virtReg) { in clearVirt() argument[all …]
155 LiveInterval &virtReg() const { in virtReg() function
39 unsigned physReg, unsigned virtReg);124 unsigned physReg, unsigned virtReg) in AddLiveIn() argument128 MRI.addLiveIn(physReg, virtReg); in AddLiveIn()131 TII->get(TargetOpcode::COPY), virtReg) in AddLiveIn()134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg)); in AddLiveIn()
102 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { in assignVirt2StackSlot() argument103 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); in assignVirt2StackSlot()104 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && in assignVirt2StackSlot()106 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); in assignVirt2StackSlot()107 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC); in assignVirt2StackSlot()110 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) { in assignVirt2StackSlot() argument111 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); in assignVirt2StackSlot()112 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && in assignVirt2StackSlot()117 Virt2StackSlotMap[virtReg] = SS; in assignVirt2StackSlot()