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Searched refs:REG_MSVDX_VEC_OFFSET (Results 1 – 4 of 4) sorted by relevance

/hardware/intel/img/psb_video/src/hwdefs/
Dmsvdx_offsets.h45 #define REG_MSVDX_VEC_MPEG2_OFFSET REG_MSVDX_VEC_OFFSET
46 #define REG_MSVDX_VEC_MPEG4_OFFSET REG_MSVDX_VEC_OFFSET
47 #define REG_MSVDX_VEC_H264_OFFSET REG_MSVDX_VEC_OFFSET
48 #define REG_MSVDX_VEC_VC1_OFFSET REG_MSVDX_VEC_OFFSET
49 #define REG_MSVDX_VEC_VP6_OFFSET REG_MSVDX_VEC_OFFSET
50 #define REG_MSVDX_VEC_VP8_OFFSET REG_MSVDX_VEC_OFFSET
51 #define REG_MSVDX_VEC_JPEG_OFFSET REG_MSVDX_VEC_OFFSET
Dmsvdx_defs.h62 #define REG_MSVDX_VEC_OFFSET 0x00000800 macro
/hardware/intel/img/psb_video/src/
Dpsb_cmdbuf.c1124 (REG_MSVDX_VEC_OFFSET + MSVDX_VEC_CR_VEC_SHIFTREG_STREAMIN_OFFSET),
Dpnw_VC1.c2326 … psb_cmdbuf_rendec_start(cmdbuf, REG_MSVDX_VEC_OFFSET + MSVDX_VEC_CR_VEC_ENTDEC_BE_CONTROL_OFFSET); in psb__VC1_load_picture_registers()