Home
last modified time | relevance | path

Searched refs:FLD_Rm (Results 1 – 5 of 5) sorted by relevance

/toolchain/binutils/binutils-2.25/opcodes/
Daarch64-opc-2.c30 …{AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer…
43 …{AARCH64_OPND_CLASS_FP_REG, "Fm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a floating-…
49 …{AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD sc…
52 …{AARCH64_OPND_CLASS_SIMD_REG, "Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD ve…
57 …{AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIM…
Daarch64-asm.c513 insert_field (FLD_Rm, code, info->addr.offset.regno, 0); in aarch64_ins_addr_regoff()
592 insert_field (FLD_Rm, code, info->addr.offset.regno, 0); in aarch64_ins_simd_addr_post()
594 insert_field (FLD_Rm, code, 0x1f, 0); in aarch64_ins_simd_addr_post()
680 insert_field (FLD_Rm, code, info->reg.regno, 0); in aarch64_ins_reg_extended()
701 insert_field (FLD_Rm, code, info->reg.regno, 0); in aarch64_ins_reg_shifted()
Daarch64-opc.h59 FLD_Rm, enumerator
Daarch64-dis.c847 info->addr.offset.regno = extract_field (FLD_Rm, code, 0); in aarch64_ext_addr_regoff()
944 info->addr.offset.regno = extract_field (FLD_Rm, code, 0); in aarch64_ext_simd_addr_post()
1081 info->reg.regno = extract_field (FLD_Rm, code, 0); in aarch64_ext_reg_extended()
1114 info->reg.regno = extract_field (FLD_Rm, code, 0); in aarch64_ext_reg_shifted()
Daarch64-tbl.h2310 Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \
2329 Y(FP_REG, regno, "Fm", 0, F(FLD_Rm), "a floating-point register") \
2335 Y(SISD_REG, regno, "Sm", 0, F(FLD_Rm), "a SIMD scalar register") \
2338 Y(SIMD_REG, regno, "Vm", 0, F(FLD_Rm), "a SIMD vector register") \
2347 Y(SIMD_ELEMENT, reglane, "Em", 0, F(FLD_Rm), \