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Searched refs:OPC1 (Results 1 – 2 of 2) sorted by relevance

/toolchain/binutils/binutils-2.25/opcodes/
Dcr16-opc.c138 #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ argument
140 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
142 {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\
150 #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ argument
152 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
294 #define CSTBIT_INST_B(NAME, OP, OPC1, OPC2, OPC3, OPC4) \ argument
300 {NAME, 2, OPC1, 24, CSTBIT_INS, {{OP,20}, {rindex7_abs20,0}}}, \
319 #define CSTBIT_INST_W(NAME, OP, OPC1, OPC2, OPC3, OPC4) \ argument
321 {NAME, 2, OPC1+6, 24, CSTBIT_INS, {{OP,20},{abs20,0}}}, \
331 {NAME, 1, OPC1+5, 24, CSTBIT_INS, {{OP,20}, {rpbase_disps0,16}}}, \
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Dcrx-opc.c87 #define SHIFT_INST(NAME, OPRD, OPC1, SHIFT1, OPC2) \ argument
91 {NAME, 1, OPC1, SHIFT1, SHIFT_INS, {{OPRD,20}, {regr,16}}}, \
157 #define CMPBR_INST(NAME, OPC1, OPC2, C4) \ argument
159 {NAME, 2, ((0x300+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3| RELAXABLE, \
162 {NAME, 3, ((0x310+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \
348 #define LD_REG_INST(NAME, OPC1, OPC2, DISP) \ argument
350 {NAME, 2, 0x320+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \
353 {NAME, 3, 0x330+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \
365 {NAME, 2, 0x32C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \
368 {NAME, 3, 0x33C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \
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