| /toolchain/binutils/binutils-2.25/opcodes/ |
| D | micromips-opc.c | 213 #define RD_2 INSN_READ_2 macro
217 #define MOD_2 (WR_2|RD_2)
290 {"prefx", "h,t(b)", 0x540001a0, 0xfc0007ff, RD_2|RD_3|FP_S|LM, 0, I1, 0, 0 },
301 {"move", "mp,mj", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 },
302 {"move", "d,s", 0x58000150, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I3, 0, 0 }, /* daddu */
303 {"move", "d,s", 0x00000150, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 }, /* addu */
304 {"move", "d,s", 0x00000290, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 }, /* or */
313 {"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
314 {"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 },
315 {"abs.ps", "T,V", 0x5400437b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
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| D | mips-opc.c | 286 #define RD_2 INSN_READ_2 macro
290 #define MOD_2 (WR_2|RD_2)
478 {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_2|RD_3|FP_S|LM, 0, I4_33, 0, I37 },
486 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I3, 0, 0 },/* daddu */
487 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 },/* addu */
488 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 },/* or */
501 {"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 },
502 {"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 },
503 {"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3, 0, IL3A, 0, 0 },
504 {"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 },
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| D | mips16-opc.c | 149 #define RD_2 INSN_READ_2 macro
153 #define MOD_2 (WR_2|RD_2)
188 {"addiu", "y,x,4", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
194 {"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
195 {"addu", "y,x,4", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
201 {"and", "x,y", 0xe80c, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
229 {"cmp", "x,y", 0xe80a, 0xf81f, RD_1|RD_2|WR_T, 0, I1, 0, 0 },
232 {"daddiu", "y,x,4", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
238 {"daddu", "z,v,y", 0xe000, 0xf803, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
239 {"daddu", "y,x,4", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
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| D | ChangeLog-2013 | 95 * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
342 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
348 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
358 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
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