1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #ifndef LLVM_LIB_TARGET_R600_AMDGPU_H 12 #define LLVM_LIB_TARGET_R600_AMDGPU_H 13 14 #include "llvm/Support/TargetRegistry.h" 15 #include "llvm/Target/TargetMachine.h" 16 17 namespace llvm { 18 19 class AMDGPUInstrPrinter; 20 class AMDGPUSubtarget; 21 class AMDGPUTargetMachine; 22 class FunctionPass; 23 class MCAsmInfo; 24 class raw_ostream; 25 class Target; 26 class TargetMachine; 27 28 // R600 Passes 29 FunctionPass *createR600VectorRegMerger(TargetMachine &tm); 30 FunctionPass *createR600TextureIntrinsicsReplacer(); 31 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm); 32 FunctionPass *createR600EmitClauseMarkers(); 33 FunctionPass *createR600ClauseMergePass(TargetMachine &tm); 34 FunctionPass *createR600Packetizer(TargetMachine &tm); 35 FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm); 36 FunctionPass *createAMDGPUCFGStructurizerPass(); 37 38 // SI Passes 39 FunctionPass *createSITypeRewriter(); 40 FunctionPass *createSIAnnotateControlFlowPass(); 41 FunctionPass *createSIFoldOperandsPass(); 42 FunctionPass *createSILowerI1CopiesPass(); 43 FunctionPass *createSIShrinkInstructionsPass(); 44 FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm); 45 FunctionPass *createSILowerControlFlowPass(TargetMachine &tm); 46 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 47 FunctionPass *createSIFixSGPRCopiesPass(); 48 FunctionPass *createSIFixSGPRLiveRangesPass(); 49 FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS); 50 FunctionPass *createSIInsertWaits(TargetMachine &tm); 51 52 ModulePass *createAMDGPUAnnotateKernelFeaturesPass(); 53 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 54 extern char &AMDGPUAnnotateKernelFeaturesID; 55 56 void initializeSIFoldOperandsPass(PassRegistry &); 57 extern char &SIFoldOperandsID; 58 59 void initializeSIFixSGPRCopiesPass(PassRegistry &); 60 extern char &SIFixSGPRCopiesID; 61 62 void initializeSILowerI1CopiesPass(PassRegistry &); 63 extern char &SILowerI1CopiesID; 64 65 void initializeSILoadStoreOptimizerPass(PassRegistry &); 66 extern char &SILoadStoreOptimizerID; 67 68 // Passes common to R600 and SI 69 FunctionPass *createAMDGPUPromoteAlloca(const AMDGPUSubtarget &ST); 70 Pass *createAMDGPUStructurizeCFGPass(); 71 FunctionPass *createAMDGPUISelDag(TargetMachine &tm); 72 ModulePass *createAMDGPUAlwaysInlinePass(); 73 ModulePass *createAMDGPUOpenCLImageTypeLoweringPass(); 74 FunctionPass *createAMDGPUAnnotateUniformValues(); 75 76 void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&); 77 extern char &SIFixControlFlowLiveIntervalsID; 78 79 void initializeSIFixSGPRLiveRangesPass(PassRegistry&); 80 extern char &SIFixSGPRLiveRangesID; 81 82 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 83 extern char &AMDGPUAnnotateUniformValuesPassID; 84 85 extern Target TheAMDGPUTarget; 86 extern Target TheGCNTarget; 87 88 namespace AMDGPU { 89 enum TargetIndex { 90 TI_CONSTDATA_START, 91 TI_SCRATCH_RSRC_DWORD0, 92 TI_SCRATCH_RSRC_DWORD1, 93 TI_SCRATCH_RSRC_DWORD2, 94 TI_SCRATCH_RSRC_DWORD3 95 }; 96 } 97 98 } // End namespace llvm 99 100 namespace ShaderType { 101 enum Type { 102 PIXEL = 0, 103 VERTEX = 1, 104 GEOMETRY = 2, 105 COMPUTE = 3 106 }; 107 } 108 109 /// OpenCL uses address spaces to differentiate between 110 /// various memory regions on the hardware. On the CPU 111 /// all of the address spaces point to the same memory, 112 /// however on the GPU, each address space points to 113 /// a separate piece of memory that is unique from other 114 /// memory locations. 115 namespace AMDGPUAS { 116 enum AddressSpaces : unsigned { 117 PRIVATE_ADDRESS = 0, ///< Address space for private memory. 118 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 119 CONSTANT_ADDRESS = 2, ///< Address space for constant memory 120 LOCAL_ADDRESS = 3, ///< Address space for local memory. 121 FLAT_ADDRESS = 4, ///< Address space for flat memory. 122 REGION_ADDRESS = 5, ///< Address space for region memory. 123 PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0) 124 PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1) 125 126 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this 127 // order to be able to dynamically index a constant buffer, for example: 128 // 129 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 130 131 CONSTANT_BUFFER_0 = 8, 132 CONSTANT_BUFFER_1 = 9, 133 CONSTANT_BUFFER_2 = 10, 134 CONSTANT_BUFFER_3 = 11, 135 CONSTANT_BUFFER_4 = 12, 136 CONSTANT_BUFFER_5 = 13, 137 CONSTANT_BUFFER_6 = 14, 138 CONSTANT_BUFFER_7 = 15, 139 CONSTANT_BUFFER_8 = 16, 140 CONSTANT_BUFFER_9 = 17, 141 CONSTANT_BUFFER_10 = 18, 142 CONSTANT_BUFFER_11 = 19, 143 CONSTANT_BUFFER_12 = 20, 144 CONSTANT_BUFFER_13 = 21, 145 CONSTANT_BUFFER_14 = 22, 146 CONSTANT_BUFFER_15 = 23, 147 ADDRESS_NONE = 24, ///< Address space for unknown memory. 148 LAST_ADDRESS = ADDRESS_NONE, 149 150 // Some places use this if the address space can't be determined. 151 UNKNOWN_ADDRESS_SPACE = ~0u 152 }; 153 154 } // namespace AMDGPUAS 155 156 #endif 157