1 //=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //==-----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
17 
18 #include "AMDGPU.h"
19 #include "AMDGPUFrameLowering.h"
20 #include "AMDGPUInstrInfo.h"
21 #include "AMDGPUISelLowering.h"
22 #include "AMDGPUSubtarget.h"
23 #include "Utils/AMDGPUBaseInfo.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
26 
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AMDGPUGenSubtargetInfo.inc"
29 
30 namespace llvm {
31 
32 class SIMachineFunctionInfo;
33 
34 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
35 
36 public:
37   enum Generation {
38     R600 = 0,
39     R700,
40     EVERGREEN,
41     NORTHERN_ISLANDS,
42     SOUTHERN_ISLANDS,
43     SEA_ISLANDS,
44     VOLCANIC_ISLANDS,
45   };
46 
47   enum {
48     FIXED_SGPR_COUNT_FOR_INIT_BUG = 80
49   };
50 
51   enum {
52     ISAVersion0_0_0,
53     ISAVersion7_0_0,
54     ISAVersion7_0_1,
55     ISAVersion8_0_0,
56     ISAVersion8_0_1
57   };
58 
59 private:
60   std::string DevName;
61   bool Is64bit;
62   bool DumpCode;
63   bool R600ALUInst;
64   bool HasVertexCache;
65   short TexVTXClauseSize;
66   Generation Gen;
67   bool FP64;
68   bool FP64Denormals;
69   bool FP32Denormals;
70   bool FastFMAF32;
71   bool CaymanISA;
72   bool FlatAddressSpace;
73   bool EnableIRStructurizer;
74   bool EnablePromoteAlloca;
75   bool EnableIfCvt;
76   bool EnableLoadStoreOpt;
77   bool EnableUnsafeDSOffsetFolding;
78   unsigned WavefrontSize;
79   bool CFALUBug;
80   int LocalMemorySize;
81   bool EnableVGPRSpilling;
82   bool SGPRInitBug;
83   bool IsGCN;
84   bool GCN1Encoding;
85   bool GCN3Encoding;
86   bool CIInsts;
87   bool FeatureDisable;
88   int LDSBankCount;
89   unsigned IsaVersion;
90   bool EnableHugeScratchBuffer;
91 
92   std::unique_ptr<AMDGPUFrameLowering> FrameLowering;
93   std::unique_ptr<AMDGPUTargetLowering> TLInfo;
94   std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
95   InstrItineraryData InstrItins;
96   Triple TargetTriple;
97 
98 public:
99   AMDGPUSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
100                   TargetMachine &TM);
101   AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
102                                                    StringRef GPU, StringRef FS);
103 
getFrameLowering()104   const AMDGPUFrameLowering *getFrameLowering() const override {
105     return FrameLowering.get();
106   }
getInstrInfo()107   const AMDGPUInstrInfo *getInstrInfo() const override {
108     return InstrInfo.get();
109   }
getRegisterInfo()110   const AMDGPURegisterInfo *getRegisterInfo() const override {
111     return &InstrInfo->getRegisterInfo();
112   }
getTargetLowering()113   AMDGPUTargetLowering *getTargetLowering() const override {
114     return TLInfo.get();
115   }
getInstrItineraryData()116   const InstrItineraryData *getInstrItineraryData() const override {
117     return &InstrItins;
118   }
119 
120   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
121 
is64bit()122   bool is64bit() const {
123     return Is64bit;
124   }
125 
hasVertexCache()126   bool hasVertexCache() const {
127     return HasVertexCache;
128   }
129 
getTexVTXClauseSize()130   short getTexVTXClauseSize() const {
131     return TexVTXClauseSize;
132   }
133 
getGeneration()134   Generation getGeneration() const {
135     return Gen;
136   }
137 
hasHWFP64()138   bool hasHWFP64() const {
139     return FP64;
140   }
141 
hasCaymanISA()142   bool hasCaymanISA() const {
143     return CaymanISA;
144   }
145 
hasFP32Denormals()146   bool hasFP32Denormals() const {
147     return FP32Denormals;
148   }
149 
hasFP64Denormals()150   bool hasFP64Denormals() const {
151     return FP64Denormals;
152   }
153 
hasFastFMAF32()154   bool hasFastFMAF32() const {
155     return FastFMAF32;
156   }
157 
hasFlatAddressSpace()158   bool hasFlatAddressSpace() const {
159     return FlatAddressSpace;
160   }
161 
hasBFE()162   bool hasBFE() const {
163     return (getGeneration() >= EVERGREEN);
164   }
165 
hasBFI()166   bool hasBFI() const {
167     return (getGeneration() >= EVERGREEN);
168   }
169 
hasBFM()170   bool hasBFM() const {
171     return hasBFE();
172   }
173 
hasBCNT(unsigned Size)174   bool hasBCNT(unsigned Size) const {
175     if (Size == 32)
176       return (getGeneration() >= EVERGREEN);
177 
178     if (Size == 64)
179       return (getGeneration() >= SOUTHERN_ISLANDS);
180 
181     return false;
182   }
183 
hasMulU24()184   bool hasMulU24() const {
185     return (getGeneration() >= EVERGREEN);
186   }
187 
hasMulI24()188   bool hasMulI24() const {
189     return (getGeneration() >= SOUTHERN_ISLANDS ||
190             hasCaymanISA());
191   }
192 
hasFFBL()193   bool hasFFBL() const {
194     return (getGeneration() >= EVERGREEN);
195   }
196 
hasFFBH()197   bool hasFFBH() const {
198     return (getGeneration() >= EVERGREEN);
199   }
200 
hasCARRY()201   bool hasCARRY() const {
202     return (getGeneration() >= EVERGREEN);
203   }
204 
hasBORROW()205   bool hasBORROW() const {
206     return (getGeneration() >= EVERGREEN);
207   }
208 
IsIRStructurizerEnabled()209   bool IsIRStructurizerEnabled() const {
210     return EnableIRStructurizer;
211   }
212 
isPromoteAllocaEnabled()213   bool isPromoteAllocaEnabled() const {
214     return EnablePromoteAlloca;
215   }
216 
isIfCvtEnabled()217   bool isIfCvtEnabled() const {
218     return EnableIfCvt;
219   }
220 
loadStoreOptEnabled()221   bool loadStoreOptEnabled() const {
222     return EnableLoadStoreOpt;
223   }
224 
unsafeDSOffsetFoldingEnabled()225   bool unsafeDSOffsetFoldingEnabled() const {
226     return EnableUnsafeDSOffsetFolding;
227   }
228 
getWavefrontSize()229   unsigned getWavefrontSize() const {
230     return WavefrontSize;
231   }
232 
233   unsigned getStackEntrySize() const;
234 
hasCFAluBug()235   bool hasCFAluBug() const {
236     assert(getGeneration() <= NORTHERN_ISLANDS);
237     return CFALUBug;
238   }
239 
getLocalMemorySize()240   int getLocalMemorySize() const {
241     return LocalMemorySize;
242   }
243 
hasSGPRInitBug()244   bool hasSGPRInitBug() const {
245     return SGPRInitBug;
246   }
247 
getLDSBankCount()248   int getLDSBankCount() const {
249     return LDSBankCount;
250   }
251 
252   unsigned getAmdKernelCodeChipID() const;
253 
254   AMDGPU::IsaVersion getIsaVersion() const;
255 
enableMachineScheduler()256   bool enableMachineScheduler() const override {
257     return true;
258   }
259 
260   void overrideSchedPolicy(MachineSchedPolicy &Policy,
261                            MachineInstr *begin, MachineInstr *end,
262                            unsigned NumRegionInstrs) const override;
263 
264   // Helper functions to simplify if statements
isTargetELF()265   bool isTargetELF() const {
266     return false;
267   }
268 
getDeviceName()269   StringRef getDeviceName() const {
270     return DevName;
271   }
272 
enableHugeScratchBuffer()273   bool enableHugeScratchBuffer() const {
274     return EnableHugeScratchBuffer;
275   }
276 
dumpCode()277   bool dumpCode() const {
278     return DumpCode;
279   }
r600ALUEncoding()280   bool r600ALUEncoding() const {
281     return R600ALUInst;
282   }
isAmdHsaOS()283   bool isAmdHsaOS() const {
284     return TargetTriple.getOS() == Triple::AMDHSA;
285   }
286   bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
287 
getMaxWavesPerCU()288   unsigned getMaxWavesPerCU() const {
289     if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
290       return 10;
291 
292     // FIXME: Not sure what this is for other subtagets.
293     llvm_unreachable("do not know max waves per CU for this subtarget.");
294   }
295 
enableSubRegLiveness()296   bool enableSubRegLiveness() const override {
297     return true;
298   }
299 
300   /// \brief Returns the offset in bytes from the start of the input buffer
301   ///        of the first explicit kernel argument.
getExplicitKernelArgOffset()302   unsigned getExplicitKernelArgOffset() const {
303     return isAmdHsaOS() ? 0 : 36;
304   }
305 
getMaxNumUserSGPRs()306   unsigned getMaxNumUserSGPRs() const {
307     return 16;
308   }
309 };
310 
311 } // End namespace llvm
312 
313 #endif
314