1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 // CPU specific code for arm independent of OS goes here.
6
7 #if V8_TARGET_ARCH_ARM64
8
9 #include "src/arm64/utils-arm64.h"
10 #include "src/assembler.h"
11
12 namespace v8 {
13 namespace internal {
14
15 class CacheLineSizes {
16 public:
CacheLineSizes()17 CacheLineSizes() {
18 #ifdef USE_SIMULATOR
19 cache_type_register_ = 0;
20 #else
21 // Copy the content of the cache type register to a core register.
22 __asm__ __volatile__ ("mrs %[ctr], ctr_el0" // NOLINT
23 : [ctr] "=r" (cache_type_register_));
24 #endif
25 }
26
icache_line_size() const27 uint32_t icache_line_size() const { return ExtractCacheLineSize(0); }
dcache_line_size() const28 uint32_t dcache_line_size() const { return ExtractCacheLineSize(16); }
29
30 private:
ExtractCacheLineSize(int cache_line_size_shift) const31 uint32_t ExtractCacheLineSize(int cache_line_size_shift) const {
32 // The cache type register holds the size of cache lines in words as a
33 // power of two.
34 return 4 << ((cache_type_register_ >> cache_line_size_shift) & 0xf);
35 }
36
37 uint32_t cache_type_register_;
38 };
39
40
FlushICache(void * address,size_t length)41 void CpuFeatures::FlushICache(void* address, size_t length) {
42 #ifdef V8_HOST_ARCH_ARM64
43 // The code below assumes user space cache operations are allowed. The goal
44 // of this routine is to make sure the code generated is visible to the I
45 // side of the CPU.
46
47 uintptr_t start = reinterpret_cast<uintptr_t>(address);
48 // Sizes will be used to generate a mask big enough to cover a pointer.
49 CacheLineSizes sizes;
50 uintptr_t dsize = sizes.dcache_line_size();
51 uintptr_t isize = sizes.icache_line_size();
52 // Cache line sizes are always a power of 2.
53 DCHECK(CountSetBits(dsize, 64) == 1);
54 DCHECK(CountSetBits(isize, 64) == 1);
55 uintptr_t dstart = start & ~(dsize - 1);
56 uintptr_t istart = start & ~(isize - 1);
57 uintptr_t end = start + length;
58
59 __asm__ __volatile__ ( // NOLINT
60 // Clean every line of the D cache containing the target data.
61 "0: \n\t"
62 // dc : Data Cache maintenance
63 // c : Clean
64 // va : by (Virtual) Address
65 // u : to the point of Unification
66 // The point of unification for a processor is the point by which the
67 // instruction and data caches are guaranteed to see the same copy of a
68 // memory location. See ARM DDI 0406B page B2-12 for more information.
69 "dc cvau, %[dline] \n\t"
70 "add %[dline], %[dline], %[dsize] \n\t"
71 "cmp %[dline], %[end] \n\t"
72 "b.lt 0b \n\t"
73 // Barrier to make sure the effect of the code above is visible to the rest
74 // of the world.
75 // dsb : Data Synchronisation Barrier
76 // ish : Inner SHareable domain
77 // The point of unification for an Inner Shareable shareability domain is
78 // the point by which the instruction and data caches of all the processors
79 // in that Inner Shareable shareability domain are guaranteed to see the
80 // same copy of a memory location. See ARM DDI 0406B page B2-12 for more
81 // information.
82 "dsb ish \n\t"
83 // Invalidate every line of the I cache containing the target data.
84 "1: \n\t"
85 // ic : instruction cache maintenance
86 // i : invalidate
87 // va : by address
88 // u : to the point of unification
89 "ic ivau, %[iline] \n\t"
90 "add %[iline], %[iline], %[isize] \n\t"
91 "cmp %[iline], %[end] \n\t"
92 "b.lt 1b \n\t"
93 // Barrier to make sure the effect of the code above is visible to the rest
94 // of the world.
95 "dsb ish \n\t"
96 // Barrier to ensure any prefetching which happened before this code is
97 // discarded.
98 // isb : Instruction Synchronisation Barrier
99 "isb \n\t"
100 : [dline] "+r" (dstart),
101 [iline] "+r" (istart)
102 : [dsize] "r" (dsize),
103 [isize] "r" (isize),
104 [end] "r" (end)
105 // This code does not write to memory but without the dependency gcc might
106 // move this code before the code is generated.
107 : "cc", "memory"
108 ); // NOLINT
109 #endif // V8_HOST_ARCH_ARM64
110 }
111
112 } // namespace internal
113 } // namespace v8
114
115 #endif // V8_TARGET_ARCH_ARM64
116