1
2 /*---------------------------------------------------------------*/
3 /*--- begin host_ppc_defs.h ---*/
4 /*---------------------------------------------------------------*/
5
6 /*
7 This file is part of Valgrind, a dynamic binary instrumentation
8 framework.
9
10 Copyright (C) 2004-2015 OpenWorks LLP
11 info@open-works.net
12
13 This program is free software; you can redistribute it and/or
14 modify it under the terms of the GNU General Public License as
15 published by the Free Software Foundation; either version 2 of the
16 License, or (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful, but
19 WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, write to the Free Software
25 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
26 02110-1301, USA.
27
28 The GNU General Public License is contained in the file COPYING.
29
30 Neither the names of the U.S. Department of Energy nor the
31 University of California nor the names of its contributors may be
32 used to endorse or promote products derived from this software
33 without prior written permission.
34 */
35
36 #ifndef __VEX_HOST_PPC_DEFS_H
37 #define __VEX_HOST_PPC_DEFS_H
38
39 #include "libvex_basictypes.h"
40 #include "libvex.h" // VexArch
41 #include "host_generic_regs.h" // HReg
42
43
44 /* --------- Registers. --------- */
45
46 #define ST_IN static inline
47
48 #define GPR(_mode64, _enc, _ix64, _ix32) \
49 mkHReg(False, (_mode64) ? HRcInt64 : HRcInt32, \
50 (_enc), (_mode64) ? (_ix64) : (_ix32))
51
52 #define FPR(_mode64, _enc, _ix64, _ix32) \
53 mkHReg(False, HRcFlt64, \
54 (_enc), (_mode64) ? (_ix64) : (_ix32))
55
56 #define VR(_mode64, _enc, _ix64, _ix32) \
57 mkHReg(False, HRcVec128, \
58 (_enc), (_mode64) ? (_ix64) : (_ix32))
59
hregPPC_GPR3(Bool mode64)60 ST_IN HReg hregPPC_GPR3 ( Bool mode64 ) { return GPR(mode64, 3, 0, 0); }
hregPPC_GPR4(Bool mode64)61 ST_IN HReg hregPPC_GPR4 ( Bool mode64 ) { return GPR(mode64, 4, 1, 1); }
hregPPC_GPR5(Bool mode64)62 ST_IN HReg hregPPC_GPR5 ( Bool mode64 ) { return GPR(mode64, 5, 2, 2); }
hregPPC_GPR6(Bool mode64)63 ST_IN HReg hregPPC_GPR6 ( Bool mode64 ) { return GPR(mode64, 6, 3, 3); }
hregPPC_GPR7(Bool mode64)64 ST_IN HReg hregPPC_GPR7 ( Bool mode64 ) { return GPR(mode64, 7, 4, 4); }
hregPPC_GPR8(Bool mode64)65 ST_IN HReg hregPPC_GPR8 ( Bool mode64 ) { return GPR(mode64, 8, 5, 5); }
hregPPC_GPR9(Bool mode64)66 ST_IN HReg hregPPC_GPR9 ( Bool mode64 ) { return GPR(mode64, 9, 6, 6); }
hregPPC_GPR10(Bool mode64)67 ST_IN HReg hregPPC_GPR10 ( Bool mode64 ) { return GPR(mode64, 10, 7, 7); }
68
69 // r11 and r12 are only allocatable in 32-bit mode. Hence the 64-bit
70 // index numbering doesn't advance for these two.
hregPPC_GPR11(Bool mode64)71 ST_IN HReg hregPPC_GPR11 ( Bool mode64 ) { return GPR(mode64, 11, 0, 8); }
hregPPC_GPR12(Bool mode64)72 ST_IN HReg hregPPC_GPR12 ( Bool mode64 ) { return GPR(mode64, 12, 0, 9); }
73
hregPPC_GPR14(Bool mode64)74 ST_IN HReg hregPPC_GPR14 ( Bool mode64 ) { return GPR(mode64, 14, 8, 10); }
hregPPC_GPR15(Bool mode64)75 ST_IN HReg hregPPC_GPR15 ( Bool mode64 ) { return GPR(mode64, 15, 9, 11); }
hregPPC_GPR16(Bool mode64)76 ST_IN HReg hregPPC_GPR16 ( Bool mode64 ) { return GPR(mode64, 16, 10, 12); }
hregPPC_GPR17(Bool mode64)77 ST_IN HReg hregPPC_GPR17 ( Bool mode64 ) { return GPR(mode64, 17, 11, 13); }
hregPPC_GPR18(Bool mode64)78 ST_IN HReg hregPPC_GPR18 ( Bool mode64 ) { return GPR(mode64, 18, 12, 14); }
hregPPC_GPR19(Bool mode64)79 ST_IN HReg hregPPC_GPR19 ( Bool mode64 ) { return GPR(mode64, 19, 13, 15); }
hregPPC_GPR20(Bool mode64)80 ST_IN HReg hregPPC_GPR20 ( Bool mode64 ) { return GPR(mode64, 20, 14, 16); }
hregPPC_GPR21(Bool mode64)81 ST_IN HReg hregPPC_GPR21 ( Bool mode64 ) { return GPR(mode64, 21, 15, 17); }
hregPPC_GPR22(Bool mode64)82 ST_IN HReg hregPPC_GPR22 ( Bool mode64 ) { return GPR(mode64, 22, 16, 18); }
hregPPC_GPR23(Bool mode64)83 ST_IN HReg hregPPC_GPR23 ( Bool mode64 ) { return GPR(mode64, 23, 17, 19); }
hregPPC_GPR24(Bool mode64)84 ST_IN HReg hregPPC_GPR24 ( Bool mode64 ) { return GPR(mode64, 24, 18, 20); }
hregPPC_GPR25(Bool mode64)85 ST_IN HReg hregPPC_GPR25 ( Bool mode64 ) { return GPR(mode64, 25, 19, 21); }
hregPPC_GPR26(Bool mode64)86 ST_IN HReg hregPPC_GPR26 ( Bool mode64 ) { return GPR(mode64, 26, 20, 22); }
hregPPC_GPR27(Bool mode64)87 ST_IN HReg hregPPC_GPR27 ( Bool mode64 ) { return GPR(mode64, 27, 21, 23); }
hregPPC_GPR28(Bool mode64)88 ST_IN HReg hregPPC_GPR28 ( Bool mode64 ) { return GPR(mode64, 28, 22, 24); }
89
hregPPC_FPR14(Bool mode64)90 ST_IN HReg hregPPC_FPR14 ( Bool mode64 ) { return FPR(mode64, 14, 23, 25); }
hregPPC_FPR15(Bool mode64)91 ST_IN HReg hregPPC_FPR15 ( Bool mode64 ) { return FPR(mode64, 15, 24, 26); }
hregPPC_FPR16(Bool mode64)92 ST_IN HReg hregPPC_FPR16 ( Bool mode64 ) { return FPR(mode64, 16, 25, 27); }
hregPPC_FPR17(Bool mode64)93 ST_IN HReg hregPPC_FPR17 ( Bool mode64 ) { return FPR(mode64, 17, 26, 28); }
hregPPC_FPR18(Bool mode64)94 ST_IN HReg hregPPC_FPR18 ( Bool mode64 ) { return FPR(mode64, 18, 27, 29); }
hregPPC_FPR19(Bool mode64)95 ST_IN HReg hregPPC_FPR19 ( Bool mode64 ) { return FPR(mode64, 19, 28, 30); }
hregPPC_FPR20(Bool mode64)96 ST_IN HReg hregPPC_FPR20 ( Bool mode64 ) { return FPR(mode64, 20, 29, 31); }
hregPPC_FPR21(Bool mode64)97 ST_IN HReg hregPPC_FPR21 ( Bool mode64 ) { return FPR(mode64, 21, 30, 32); }
98
hregPPC_VR20(Bool mode64)99 ST_IN HReg hregPPC_VR20 ( Bool mode64 ) { return VR (mode64, 20, 31, 33); }
hregPPC_VR21(Bool mode64)100 ST_IN HReg hregPPC_VR21 ( Bool mode64 ) { return VR (mode64, 21, 32, 34); }
hregPPC_VR22(Bool mode64)101 ST_IN HReg hregPPC_VR22 ( Bool mode64 ) { return VR (mode64, 22, 33, 35); }
hregPPC_VR23(Bool mode64)102 ST_IN HReg hregPPC_VR23 ( Bool mode64 ) { return VR (mode64, 23, 34, 36); }
hregPPC_VR24(Bool mode64)103 ST_IN HReg hregPPC_VR24 ( Bool mode64 ) { return VR (mode64, 24, 35, 37); }
hregPPC_VR25(Bool mode64)104 ST_IN HReg hregPPC_VR25 ( Bool mode64 ) { return VR (mode64, 25, 36, 38); }
hregPPC_VR26(Bool mode64)105 ST_IN HReg hregPPC_VR26 ( Bool mode64 ) { return VR (mode64, 26, 37, 39); }
hregPPC_VR27(Bool mode64)106 ST_IN HReg hregPPC_VR27 ( Bool mode64 ) { return VR (mode64, 27, 38, 40); }
107
hregPPC_GPR1(Bool mode64)108 ST_IN HReg hregPPC_GPR1 ( Bool mode64 ) { return GPR(mode64, 1, 39, 41); }
hregPPC_GPR29(Bool mode64)109 ST_IN HReg hregPPC_GPR29 ( Bool mode64 ) { return GPR(mode64, 29, 40, 42); }
hregPPC_GPR30(Bool mode64)110 ST_IN HReg hregPPC_GPR30 ( Bool mode64 ) { return GPR(mode64, 30, 41, 43); }
hregPPC_GPR31(Bool mode64)111 ST_IN HReg hregPPC_GPR31 ( Bool mode64 ) { return GPR(mode64, 31, 42, 44); }
hregPPC_VR29(Bool mode64)112 ST_IN HReg hregPPC_VR29 ( Bool mode64 ) { return VR (mode64, 29, 43, 45); }
113
114 #undef ST_IN
115 #undef GPR
116 #undef FPR
117 #undef VR
118
119 #define StackFramePtr(_mode64) hregPPC_GPR1(_mode64)
120 #define GuestStatePtr(_mode64) hregPPC_GPR31(_mode64)
121
122 /* Num registers used for function calls */
123 #define PPC_N_REGPARMS 8
124
125 extern void ppHRegPPC ( HReg );
126
127
128 /* --------- Condition codes --------- */
129
130 /* This gives names from bitfields in CR; hence it names BI numbers */
131 /* Using IBM/hardware indexing convention */
132 typedef
133 enum {
134 // CR7, which we use for integer compares
135 Pcf_7LT = 28, /* neg | lt */
136 Pcf_7GT = 29, /* pos | gt */
137 Pcf_7EQ = 30, /* zero | equal */
138 Pcf_7SO = 31, /* summary overflow */
139 Pcf_NONE = 32 /* no condition; used with Pct_ALWAYS */
140 }
141 PPCCondFlag;
142
143 typedef
144 enum { /* Maps bc bitfield BO */
145 Pct_FALSE = 0x4, /* associated PPCCondFlag must not be Pcf_NONE */
146 Pct_TRUE = 0xC, /* associated PPCCondFlag must not be Pcf_NONE */
147 Pct_ALWAYS = 0x14 /* associated PPCCondFlag must be Pcf_NONE */
148 }
149 PPCCondTest;
150
151 typedef
152 struct {
153 PPCCondFlag flag;
154 PPCCondTest test;
155 }
156 PPCCondCode;
157
158 extern const HChar* showPPCCondCode ( PPCCondCode );
159
160 /* constructor */
161 extern PPCCondCode mk_PPCCondCode ( PPCCondTest, PPCCondFlag );
162
163 /* false->true, true->false */
164 extern PPCCondTest invertCondTest ( PPCCondTest );
165
166
167
168
169 /* --------- Memory address expressions (amodes). --------- */
170
171 typedef
172 enum {
173 Pam_IR=1, /* Immediate (signed 16-bit) + Reg */
174 Pam_RR=2 /* Reg1 + Reg2 */
175 }
176 PPCAModeTag;
177
178 typedef
179 struct {
180 PPCAModeTag tag;
181 union {
182 struct {
183 HReg base;
184 Int index;
185 } IR;
186 struct {
187 HReg base;
188 HReg index;
189 } RR;
190 } Pam;
191 }
192 PPCAMode;
193
194 extern PPCAMode* PPCAMode_IR ( Int, HReg );
195 extern PPCAMode* PPCAMode_RR ( HReg, HReg );
196
197 extern PPCAMode* dopyPPCAMode ( PPCAMode* );
198
199 extern void ppPPCAMode ( PPCAMode* );
200
201
202 /* --------- Operand, which can be a reg or a u16/s16. --------- */
203 /* ("RH" == "Register or Halfword immediate") */
204 typedef
205 enum {
206 Prh_Imm=3,
207 Prh_Reg=4
208 }
209 PPCRHTag;
210
211 typedef
212 struct {
213 PPCRHTag tag;
214 union {
215 struct {
216 Bool syned;
217 UShort imm16;
218 } Imm;
219 struct {
220 HReg reg;
221 } Reg;
222 }
223 Prh;
224 }
225 PPCRH;
226
227 extern PPCRH* PPCRH_Imm ( Bool, UShort );
228 extern PPCRH* PPCRH_Reg ( HReg );
229
230 extern void ppPPCRH ( PPCRH* );
231
232
233 /* --------- Operand, which can be a reg or a u32/64. --------- */
234
235 typedef
236 enum {
237 Pri_Imm=5,
238 Pri_Reg=6
239 }
240 PPCRITag;
241
242 typedef
243 struct {
244 PPCRITag tag;
245 union {
246 ULong Imm;
247 HReg Reg;
248 }
249 Pri;
250 }
251 PPCRI;
252
253 extern PPCRI* PPCRI_Imm ( ULong );
254 extern PPCRI* PPCRI_Reg( HReg );
255
256 extern void ppPPCRI ( PPCRI* );
257
258
259 /* --------- Operand, which can be a vector reg or a s6. --------- */
260 /* ("VI" == "Vector Register or Immediate") */
261 typedef
262 enum {
263 Pvi_Imm=7,
264 Pvi_Reg=8
265 }
266 PPCVI5sTag;
267
268 typedef
269 struct {
270 PPCVI5sTag tag;
271 union {
272 Char Imm5s;
273 HReg Reg;
274 }
275 Pvi;
276 }
277 PPCVI5s;
278
279 extern PPCVI5s* PPCVI5s_Imm ( Char );
280 extern PPCVI5s* PPCVI5s_Reg ( HReg );
281
282 extern void ppPPCVI5s ( PPCVI5s* );
283
284
285 /* --------- Instructions. --------- */
286
287 /* --------- */
288 typedef
289 enum {
290 Pun_NEG,
291 Pun_NOT,
292 Pun_CLZ32,
293 Pun_CLZ64,
294 Pun_EXTSW
295 }
296 PPCUnaryOp;
297
298 extern const HChar* showPPCUnaryOp ( PPCUnaryOp );
299
300
301 /* --------- */
302 typedef
303 enum {
304 Palu_INVALID,
305 Palu_ADD, Palu_SUB,
306 Palu_AND, Palu_OR, Palu_XOR,
307 }
308 PPCAluOp;
309
310 extern
311 const HChar* showPPCAluOp ( PPCAluOp,
312 Bool /* is the 2nd operand an immediate? */);
313
314
315 /* --------- */
316 typedef
317 enum {
318 Pshft_INVALID,
319 Pshft_SHL, Pshft_SHR, Pshft_SAR,
320 }
321 PPCShftOp;
322
323 extern
324 const HChar* showPPCShftOp ( PPCShftOp,
325 Bool /* is the 2nd operand an immediate? */,
326 Bool /* is this a 32bit or 64bit op? */ );
327
328
329 /* --------- */
330 typedef
331 enum {
332 Pfp_INVALID,
333
334 /* Ternary */
335 Pfp_MADDD, Pfp_MSUBD,
336 Pfp_MADDS, Pfp_MSUBS,
337 Pfp_DFPADD, Pfp_DFPADDQ,
338 Pfp_DFPSUB, Pfp_DFPSUBQ,
339 Pfp_DFPMUL, Pfp_DFPMULQ,
340 Pfp_DFPDIV, Pfp_DFPDIVQ,
341 Pfp_DQUAQ, Pfp_DRRNDQ,
342
343 /* Binary */
344 Pfp_ADDD, Pfp_SUBD, Pfp_MULD, Pfp_DIVD,
345 Pfp_ADDS, Pfp_SUBS, Pfp_MULS, Pfp_DIVS,
346 Pfp_DRSP, Pfp_DRDPQ, Pfp_DCTFIX, Pfp_DCTFIXQ, Pfp_DCFFIX,
347 Pfp_DQUA, Pfp_RRDTR, Pfp_DIEX, Pfp_DIEXQ, Pfp_DRINTN,
348
349 /* Unary */
350 Pfp_SQRT, Pfp_ABS, Pfp_NEG, Pfp_MOV, Pfp_RES, Pfp_RSQRTE,
351 Pfp_FRIN, Pfp_FRIM, Pfp_FRIP, Pfp_FRIZ,
352 Pfp_DSCLI, Pfp_DSCRI, Pfp_DSCLIQ, Pfp_DSCRIQ, Pfp_DCTDP,
353 Pfp_DCTQPQ, Pfp_DCFFIXQ, Pfp_DXEX, Pfp_DXEXQ,
354
355 }
356 PPCFpOp;
357
358 extern const HChar* showPPCFpOp ( PPCFpOp );
359
360
361 /* --------- */
362 typedef
363 enum {
364 Pav_INVALID,
365
366 /* Integer Unary */
367 Pav_MOV, /* Mov */
368 Pav_NOT, /* Bitwise */
369 Pav_UNPCKH8S, Pav_UNPCKH16S, /* Unpack */
370 Pav_UNPCKL8S, Pav_UNPCKL16S,
371 Pav_UNPCKHPIX, Pav_UNPCKLPIX,
372
373 /* Integer Binary */
374 Pav_AND, Pav_OR, Pav_XOR, /* Bitwise */
375 Pav_ADDU, Pav_QADDU, Pav_QADDS,
376 Pav_SUBU, Pav_QSUBU, Pav_QSUBS,
377 Pav_MULU,
378 Pav_OMULU, Pav_OMULS, Pav_EMULU, Pav_EMULS,
379 Pav_AVGU, Pav_AVGS,
380 Pav_MAXU, Pav_MAXS,
381 Pav_MINU, Pav_MINS,
382
383 /* Compare (always affects CR field 6) */
384 Pav_CMPEQU, Pav_CMPGTU, Pav_CMPGTS,
385
386 /* Shift */
387 Pav_SHL, Pav_SHR, Pav_SAR, Pav_ROTL,
388
389 /* Pack */
390 Pav_PACKUU, Pav_QPACKUU, Pav_QPACKSU, Pav_QPACKSS,
391 Pav_PACKPXL,
392
393 /* Merge */
394 Pav_MRGHI, Pav_MRGLO,
395
396 /* Concatenation */
397 Pav_CATODD, Pav_CATEVEN,
398
399 /* Polynomial Multipy-Add */
400 Pav_POLYMULADD,
401
402 /* Cipher */
403 Pav_CIPHERV128, Pav_CIPHERLV128, Pav_NCIPHERV128, Pav_NCIPHERLV128,
404 Pav_CIPHERSUBV128,
405
406 /* Hash */
407 Pav_SHA256, Pav_SHA512,
408
409 /* BCD Arithmetic */
410 Pav_BCDAdd, Pav_BCDSub,
411
412 /* zero count */
413 Pav_ZEROCNTBYTE, Pav_ZEROCNTWORD, Pav_ZEROCNTHALF, Pav_ZEROCNTDBL,
414
415 /* Vector bit matrix transpose by byte */
416 Pav_BITMTXXPOSE,
417 }
418 PPCAvOp;
419
420 extern const HChar* showPPCAvOp ( PPCAvOp );
421
422
423 /* --------- */
424 typedef
425 enum {
426 Pavfp_INVALID,
427
428 /* Floating point binary */
429 Pavfp_ADDF, Pavfp_SUBF, Pavfp_MULF,
430 Pavfp_MAXF, Pavfp_MINF,
431 Pavfp_CMPEQF, Pavfp_CMPGTF, Pavfp_CMPGEF,
432
433 /* Floating point unary */
434 Pavfp_RCPF, Pavfp_RSQRTF,
435 Pavfp_CVTU2F, Pavfp_CVTS2F, Pavfp_QCVTF2U, Pavfp_QCVTF2S,
436 Pavfp_ROUNDM, Pavfp_ROUNDP, Pavfp_ROUNDN, Pavfp_ROUNDZ,
437 }
438 PPCAvFpOp;
439
440 extern const HChar* showPPCAvFpOp ( PPCAvFpOp );
441
442
443 /* --------- */
444 typedef
445 enum {
446 Pin_LI, /* load word (32/64-bit) immediate (fake insn) */
447 Pin_Alu, /* word add/sub/and/or/xor */
448 Pin_Shft, /* word shl/shr/sar */
449 Pin_AddSubC, /* add/sub with read/write carry */
450 Pin_Cmp, /* word compare */
451 Pin_Unary, /* not, neg, clz */
452 Pin_MulL, /* widening multiply */
453 Pin_Div, /* div */
454 Pin_Call, /* call to address in register */
455 Pin_XDirect, /* direct transfer to GA */
456 Pin_XIndir, /* indirect transfer to GA */
457 Pin_XAssisted, /* assisted transfer to GA */
458 Pin_CMov, /* conditional move */
459 Pin_Load, /* zero-extending load a 8|16|32|64 bit value from mem */
460 Pin_LoadL, /* load-linked (lwarx/ldarx) 32|64 bit value from mem */
461 Pin_Store, /* store a 8|16|32|64 bit value to mem */
462 Pin_StoreC, /* store-conditional (stwcx./stdcx.) 32|64 bit val */
463 Pin_Set, /* convert condition code to value 0 or 1 */
464 Pin_MfCR, /* move from condition register to GPR */
465 Pin_MFence, /* mem fence */
466
467 Pin_FpUnary, /* FP unary op */
468 Pin_FpBinary, /* FP binary op */
469 Pin_FpMulAcc, /* FP multipy-accumulate style op */
470 Pin_FpLdSt, /* FP load/store */
471 Pin_FpSTFIW, /* stfiwx */
472 Pin_FpRSP, /* FP round IEEE754 double to IEEE754 single */
473 Pin_FpCftI, /* fcfid[u,s,us]/fctid[u]/fctiw[u] */
474 Pin_FpCMov, /* FP floating point conditional move */
475 Pin_FpLdFPSCR, /* mtfsf */
476 Pin_FpCmp, /* FP compare, generating value into int reg */
477
478 Pin_RdWrLR, /* Read/Write Link Register */
479
480 Pin_AvLdSt, /* AV load/store (kludging for AMode_IR) */
481 Pin_AvUnary, /* AV unary general reg=>reg */
482
483 Pin_AvBinary, /* AV binary general reg,reg=>reg */
484 Pin_AvBin8x16, /* AV binary, 8x4 */
485 Pin_AvBin16x8, /* AV binary, 16x4 */
486 Pin_AvBin32x4, /* AV binary, 32x4 */
487 Pin_AvBin64x2, /* AV binary, 64x2 */
488
489 Pin_AvBin32Fx4, /* AV FP binary, 32Fx4 */
490 Pin_AvUn32Fx4, /* AV FP unary, 32Fx4 */
491
492 Pin_AvPerm, /* AV permute (shuffle) */
493 Pin_AvSel, /* AV select */
494 Pin_AvSh, /* AV shift left or right */
495 Pin_AvShlDbl, /* AV shift-left double by imm */
496 Pin_AvSplat, /* One elem repeated throughout dst */
497 Pin_AvLdVSCR, /* mtvscr */
498 Pin_AvCMov, /* AV conditional move */
499 Pin_AvCipherV128Unary, /* AV Vector unary Cipher */
500 Pin_AvCipherV128Binary, /* AV Vector binary Cipher */
501 Pin_AvHashV128Binary, /* AV Vector binary Hash */
502 Pin_AvBCDV128Trinary, /* BCD Arithmetic */
503 Pin_Dfp64Unary, /* DFP64 unary op */
504 Pin_Dfp128Unary, /* DFP128 unary op */
505 Pin_DfpShift, /* Decimal floating point shift by immediate value */
506 Pin_Dfp64Binary, /* DFP64 binary op */
507 Pin_Dfp128Binary, /* DFP128 binary op */
508 Pin_DfpShift128, /* 128-bit Decimal floating point shift by
509 * immediate value */
510 Pin_DfpD128toD64, /* DFP 128 to DFP 64 op */
511 Pin_DfpI64StoD128, /* DFP signed integer to DFP 128 */
512 Pin_DfpRound, /* D64 round to D64 */
513 Pin_DfpRound128, /* D128 round to D128 */
514 Pin_ExtractExpD128, /* DFP, extract 64 bit exponent */
515 Pin_InsertExpD128, /* DFP, insert 64 bit exponent and 128 bit binary
516 * significand into a DFP 128-bit value*/
517 Pin_Dfp64Cmp, /* DFP 64-bit compare, generating value into
518 * int reg */
519 Pin_Dfp128Cmp, /* DFP 128-bit compare, generating value into
520 * int reg */
521 Pin_DfpQuantize, /* D64 quantize using register value, significance
522 * round */
523 Pin_DfpQuantize128, /* D128 quantize using register value, significance
524 * round */
525 Pin_EvCheck, /* Event check */
526 Pin_ProfInc /* 64-bit profile counter increment */
527 }
528 PPCInstrTag;
529
530 /* Destinations are on the LEFT (first operand) */
531
532 typedef
533 struct {
534 PPCInstrTag tag;
535 union {
536 /* Get a 32/64-bit literal into a register.
537 May turn into a number of real insns. */
538 struct {
539 HReg dst;
540 ULong imm64;
541 } LI;
542 /* Integer add/sub/and/or/xor. Limitations:
543 - For add, the immediate, if it exists, is a signed 16.
544 - For sub, the immediate, if it exists, is a signed 16
545 which may not be -32768, since no such instruction
546 exists, and so we have to emit addi with +32768, but
547 that is not possible.
548 - For and/or/xor, the immediate, if it exists,
549 is an unsigned 16.
550 */
551 struct {
552 PPCAluOp op;
553 HReg dst;
554 HReg srcL;
555 PPCRH* srcR;
556 } Alu;
557 /* Integer shl/shr/sar.
558 Limitations: the immediate, if it exists,
559 is a signed 5-bit value between 1 and 31 inclusive.
560 */
561 struct {
562 PPCShftOp op;
563 Bool sz32; /* mode64 has both 32 and 64bit shft */
564 HReg dst;
565 HReg srcL;
566 PPCRH* srcR;
567 } Shft;
568 /* */
569 struct {
570 Bool isAdd; /* else sub */
571 Bool setC; /* else read carry */
572 HReg dst;
573 HReg srcL;
574 HReg srcR;
575 } AddSubC;
576 /* If signed, the immediate, if it exists, is a signed 16,
577 else it is an unsigned 16. */
578 struct {
579 Bool syned;
580 Bool sz32; /* mode64 has both 32 and 64bit cmp */
581 UInt crfD;
582 HReg srcL;
583 PPCRH* srcR;
584 } Cmp;
585 /* Not, Neg, Clz32/64, Extsw */
586 struct {
587 PPCUnaryOp op;
588 HReg dst;
589 HReg src;
590 } Unary;
591 struct {
592 Bool syned; /* meaningless if hi32==False */
593 Bool hi; /* False=>low, True=>high */
594 Bool sz32; /* mode64 has both 32 & 64bit mull */
595 HReg dst;
596 HReg srcL;
597 HReg srcR;
598 } MulL;
599 /* ppc32 div/divu instruction. */
600 struct {
601 Bool extended;
602 Bool syned;
603 Bool sz32; /* mode64 has both 32 & 64bit div */
604 HReg dst;
605 HReg srcL;
606 HReg srcR;
607 } Div;
608 /* Pseudo-insn. Call target (an absolute address), on given
609 condition (which could be Pct_ALWAYS). argiregs indicates
610 which of r3 .. r10 carries argument values for this call,
611 using a bit mask (1<<N is set if rN holds an arg, for N in
612 3 .. 10 inclusive). */
613 struct {
614 PPCCondCode cond;
615 Addr64 target;
616 UInt argiregs;
617 RetLoc rloc; /* where the return value will be */
618 } Call;
619 /* Update the guest CIA value, then exit requesting to chain
620 to it. May be conditional. Use of Addr64 in order to cope
621 with 64-bit hosts. */
622 struct {
623 Addr64 dstGA; /* next guest address */
624 PPCAMode* amCIA; /* amode in guest state for CIA */
625 PPCCondCode cond; /* can be ALWAYS */
626 Bool toFastEP; /* chain to the slow or fast point? */
627 } XDirect;
628 /* Boring transfer to a guest address not known at JIT time.
629 Not chainable. May be conditional. */
630 struct {
631 HReg dstGA;
632 PPCAMode* amCIA;
633 PPCCondCode cond; /* can be ALWAYS */
634 } XIndir;
635 /* Assisted transfer to a guest address, most general case.
636 Not chainable. May be conditional. */
637 struct {
638 HReg dstGA;
639 PPCAMode* amCIA;
640 PPCCondCode cond; /* can be ALWAYS */
641 IRJumpKind jk;
642 } XAssisted;
643 /* Mov src to dst on the given condition, which may not
644 be the bogus Pct_ALWAYS. */
645 struct {
646 PPCCondCode cond;
647 HReg dst;
648 PPCRI* src;
649 } CMov;
650 /* Zero extending loads. Dst size is host word size */
651 struct {
652 UChar sz; /* 1|2|4|8 */
653 HReg dst;
654 PPCAMode* src;
655 } Load;
656 /* Load-and-reserve (lwarx, ldarx) */
657 struct {
658 UChar sz; /* 4|8 */
659 HReg dst;
660 HReg src;
661 } LoadL;
662 /* 64/32/16/8 bit stores */
663 struct {
664 UChar sz; /* 1|2|4|8 */
665 PPCAMode* dst;
666 HReg src;
667 } Store;
668 /* Store-conditional (stwcx., stdcx.) */
669 struct {
670 UChar sz; /* 4|8 */
671 HReg dst;
672 HReg src;
673 } StoreC;
674 /* Convert a ppc condition code to value 0 or 1. */
675 struct {
676 PPCCondCode cond;
677 HReg dst;
678 } Set;
679 /* Move the entire CR to a GPR */
680 struct {
681 HReg dst;
682 } MfCR;
683 /* Mem fence. In short, an insn which flushes all preceding
684 loads and stores as much as possible before continuing.
685 On PPC we emit a "sync". */
686 struct {
687 } MFence;
688
689 /* PPC Floating point */
690 struct {
691 PPCFpOp op;
692 HReg dst;
693 HReg src;
694 } FpUnary;
695 struct {
696 PPCFpOp op;
697 HReg dst;
698 HReg srcL;
699 HReg srcR;
700 } FpBinary;
701 struct {
702 PPCFpOp op;
703 HReg dst;
704 HReg srcML;
705 HReg srcMR;
706 HReg srcAcc;
707 } FpMulAcc;
708 struct {
709 Bool isLoad;
710 UChar sz; /* only 4 (IEEE single) or 8 (IEEE double) */
711 HReg reg;
712 PPCAMode* addr;
713 } FpLdSt;
714 struct {
715 HReg addr; /* int reg */
716 HReg data; /* float reg */
717 } FpSTFIW;
718 /* Round 64-bit FP value to 32-bit FP value in an FP reg. */
719 struct {
720 HReg src;
721 HReg dst;
722 } FpRSP;
723 /* fcfid[u,s,us]/fctid[u]/fctiw[u]. Only some combinations
724 of the various fields are allowed. This is asserted for
725 and documented in the code for the constructor,
726 PPCInstr_FpCftI, in host_ppc_defs.c. */
727 struct {
728 Bool fromI; /* True== I->F, False== F->I */
729 Bool int32; /* True== I is 32, False== I is 64 */
730 Bool syned;
731 Bool flt64; /* True== F is 64, False== F is 32 */
732 HReg src;
733 HReg dst;
734 } FpCftI;
735 /* FP mov src to dst on the given condition. */
736 struct {
737 PPCCondCode cond;
738 HReg dst;
739 HReg src;
740 } FpCMov;
741 /* Load FP Status & Control Register */
742 struct {
743 HReg src;
744 UInt dfp_rm;
745 } FpLdFPSCR;
746 /* Do a compare, generating result into an int register. */
747 struct {
748 UChar crfD;
749 HReg dst;
750 HReg srcL;
751 HReg srcR;
752 } FpCmp;
753
754 /* Read/Write Link Register */
755 struct {
756 Bool wrLR;
757 HReg gpr;
758 } RdWrLR;
759
760 /* Simplistic AltiVec */
761 struct {
762 Bool isLoad;
763 UChar sz; /* 8|16|32|128 */
764 HReg reg;
765 PPCAMode* addr;
766 } AvLdSt;
767 struct {
768 PPCAvOp op;
769 HReg dst;
770 HReg src;
771 } AvUnary;
772 struct {
773 PPCAvOp op;
774 HReg dst;
775 HReg srcL;
776 HReg srcR;
777 } AvBinary;
778 struct {
779 PPCAvOp op;
780 HReg dst;
781 HReg srcL;
782 HReg srcR;
783 } AvBin8x16;
784 struct {
785 PPCAvOp op;
786 HReg dst;
787 HReg srcL;
788 HReg srcR;
789 } AvBin16x8;
790 struct {
791 PPCAvOp op;
792 HReg dst;
793 HReg srcL;
794 HReg srcR;
795 } AvBin32x4;
796 /* Can only be generated for CPUs capable of ISA 2.07 or above */
797 struct {
798 PPCAvOp op;
799 HReg dst;
800 HReg srcL;
801 HReg srcR;
802 } AvBin64x2;
803 struct {
804 PPCAvFpOp op;
805 HReg dst;
806 HReg srcL;
807 HReg srcR;
808 } AvBin32Fx4;
809 struct {
810 PPCAvFpOp op;
811 HReg dst;
812 HReg src;
813 } AvUn32Fx4;
814 /* Perm,Sel,SlDbl,Splat are all weird AV permutations */
815 struct {
816 HReg dst;
817 HReg srcL;
818 HReg srcR;
819 HReg ctl;
820 } AvPerm;
821 struct {
822 HReg dst;
823 HReg srcL;
824 HReg srcR;
825 HReg ctl;
826 } AvSel;
827 struct {
828 Bool shLeft;
829 HReg dst;
830 PPCAMode* addr;
831 } AvSh;
832 struct {
833 UChar shift;
834 HReg dst;
835 HReg srcL;
836 HReg srcR;
837 } AvShlDbl;
838 struct {
839 UChar sz; /* 8,16,32 */
840 HReg dst;
841 PPCVI5s* src;
842 } AvSplat;
843 /* Mov src to dst on the given condition, which may not
844 be the bogus Xcc_ALWAYS. */
845 struct {
846 PPCCondCode cond;
847 HReg dst;
848 HReg src;
849 } AvCMov;
850 /* Load AltiVec Status & Control Register */
851 struct {
852 HReg src;
853 } AvLdVSCR;
854 struct {
855 PPCAvOp op;
856 HReg dst;
857 HReg src;
858 } AvCipherV128Unary;
859 struct {
860 PPCAvOp op;
861 HReg dst;
862 HReg src;
863 PPCRI* s_field;
864 } AvHashV128Binary;
865 struct {
866 PPCAvOp op;
867 HReg dst;
868 HReg src1;
869 HReg src2;
870 PPCRI* ps;
871 } AvBCDV128Trinary;
872 struct {
873 PPCAvOp op;
874 HReg dst;
875 HReg srcL;
876 HReg srcR;
877 } AvCipherV128Binary;
878 struct {
879 PPCFpOp op;
880 HReg dst;
881 HReg src;
882 } Dfp64Unary;
883 struct {
884 PPCFpOp op;
885 HReg dst;
886 HReg srcL;
887 HReg srcR;
888 } Dfp64Binary;
889 struct {
890 PPCFpOp op;
891 HReg dst;
892 HReg src;
893 PPCRI* shift;
894 } DfpShift;
895 struct {
896 PPCFpOp op;
897 HReg dst_hi;
898 HReg dst_lo;
899 HReg src_hi;
900 HReg src_lo;
901 } Dfp128Unary;
902 struct {
903 /* The dst is used to pass the left source operand in and return
904 * the result.
905 */
906 PPCFpOp op;
907 HReg dst_hi;
908 HReg dst_lo;
909 HReg srcR_hi;
910 HReg srcR_lo;
911 } Dfp128Binary;
912 struct {
913 PPCFpOp op;
914 HReg dst_hi;
915 HReg dst_lo;
916 HReg src_hi;
917 HReg src_lo;
918 PPCRI* shift;
919 } DfpShift128;
920 struct {
921 HReg dst;
922 HReg src;
923 PPCRI* r_rmc;
924 } DfpRound;
925 struct {
926 HReg dst_hi;
927 HReg dst_lo;
928 HReg src_hi;
929 HReg src_lo;
930 PPCRI* r_rmc;
931 } DfpRound128;
932 struct {
933 PPCFpOp op;
934 HReg dst;
935 HReg srcL;
936 HReg srcR;
937 PPCRI* rmc;
938 } DfpQuantize;
939 struct {
940 PPCFpOp op;
941 HReg dst_hi;
942 HReg dst_lo;
943 HReg src_hi;
944 HReg src_lo;
945 PPCRI* rmc;
946 } DfpQuantize128;
947 struct {
948 PPCFpOp op;
949 HReg dst;
950 HReg src_hi;
951 HReg src_lo;
952 } ExtractExpD128;
953 struct {
954 PPCFpOp op;
955 HReg dst_hi;
956 HReg dst_lo;
957 HReg srcL;
958 HReg srcR_hi;
959 HReg srcR_lo;
960 } InsertExpD128;
961 struct {
962 PPCFpOp op;
963 HReg dst;
964 HReg src_hi;
965 HReg src_lo;
966 } DfpD128toD64;
967 struct {
968 PPCFpOp op;
969 HReg dst_hi;
970 HReg dst_lo;
971 HReg src;
972 } DfpI64StoD128;
973 struct {
974 UChar crfD;
975 HReg dst;
976 HReg srcL;
977 HReg srcR;
978 } Dfp64Cmp;
979 struct {
980 UChar crfD;
981 HReg dst;
982 HReg srcL_hi;
983 HReg srcL_lo;
984 HReg srcR_hi;
985 HReg srcR_lo;
986 } Dfp128Cmp;
987 struct {
988 PPCAMode* amCounter;
989 PPCAMode* amFailAddr;
990 } EvCheck;
991 struct {
992 /* No fields. The address of the counter to inc is
993 installed later, post-translation, by patching it in,
994 as it is not known at translation time. */
995 } ProfInc;
996 } Pin;
997 }
998 PPCInstr;
999
1000
1001 extern PPCInstr* PPCInstr_LI ( HReg, ULong, Bool );
1002 extern PPCInstr* PPCInstr_Alu ( PPCAluOp, HReg, HReg, PPCRH* );
1003 extern PPCInstr* PPCInstr_Shft ( PPCShftOp, Bool sz32, HReg, HReg, PPCRH* );
1004 extern PPCInstr* PPCInstr_AddSubC ( Bool, Bool, HReg, HReg, HReg );
1005 extern PPCInstr* PPCInstr_Cmp ( Bool, Bool, UInt, HReg, PPCRH* );
1006 extern PPCInstr* PPCInstr_Unary ( PPCUnaryOp op, HReg dst, HReg src );
1007 extern PPCInstr* PPCInstr_MulL ( Bool syned, Bool hi32, Bool sz32, HReg, HReg, HReg );
1008 extern PPCInstr* PPCInstr_Div ( Bool extended, Bool syned, Bool sz32, HReg dst, HReg srcL, HReg srcR );
1009 extern PPCInstr* PPCInstr_Call ( PPCCondCode, Addr64, UInt, RetLoc );
1010 extern PPCInstr* PPCInstr_XDirect ( Addr64 dstGA, PPCAMode* amCIA,
1011 PPCCondCode cond, Bool toFastEP );
1012 extern PPCInstr* PPCInstr_XIndir ( HReg dstGA, PPCAMode* amCIA,
1013 PPCCondCode cond );
1014 extern PPCInstr* PPCInstr_XAssisted ( HReg dstGA, PPCAMode* amCIA,
1015 PPCCondCode cond, IRJumpKind jk );
1016 extern PPCInstr* PPCInstr_CMov ( PPCCondCode, HReg dst, PPCRI* src );
1017 extern PPCInstr* PPCInstr_Load ( UChar sz,
1018 HReg dst, PPCAMode* src, Bool mode64 );
1019 extern PPCInstr* PPCInstr_LoadL ( UChar sz,
1020 HReg dst, HReg src, Bool mode64 );
1021 extern PPCInstr* PPCInstr_Store ( UChar sz, PPCAMode* dst,
1022 HReg src, Bool mode64 );
1023 extern PPCInstr* PPCInstr_StoreC ( UChar sz, HReg dst, HReg src,
1024 Bool mode64 );
1025 extern PPCInstr* PPCInstr_Set ( PPCCondCode cond, HReg dst );
1026 extern PPCInstr* PPCInstr_MfCR ( HReg dst );
1027 extern PPCInstr* PPCInstr_MFence ( void );
1028
1029 extern PPCInstr* PPCInstr_FpUnary ( PPCFpOp op, HReg dst, HReg src );
1030 extern PPCInstr* PPCInstr_FpBinary ( PPCFpOp op, HReg dst, HReg srcL, HReg srcR );
1031 extern PPCInstr* PPCInstr_FpMulAcc ( PPCFpOp op, HReg dst, HReg srcML,
1032 HReg srcMR, HReg srcAcc );
1033 extern PPCInstr* PPCInstr_FpLdSt ( Bool isLoad, UChar sz, HReg, PPCAMode* );
1034 extern PPCInstr* PPCInstr_FpSTFIW ( HReg addr, HReg data );
1035 extern PPCInstr* PPCInstr_FpRSP ( HReg dst, HReg src );
1036 extern PPCInstr* PPCInstr_FpCftI ( Bool fromI, Bool int32, Bool syned,
1037 Bool dst64, HReg dst, HReg src );
1038 extern PPCInstr* PPCInstr_FpCMov ( PPCCondCode, HReg dst, HReg src );
1039 extern PPCInstr* PPCInstr_FpLdFPSCR ( HReg src, Bool dfp_rm );
1040 extern PPCInstr* PPCInstr_FpCmp ( HReg dst, HReg srcL, HReg srcR );
1041
1042 extern PPCInstr* PPCInstr_RdWrLR ( Bool wrLR, HReg gpr );
1043
1044 extern PPCInstr* PPCInstr_AvLdSt ( Bool isLoad, UChar sz, HReg, PPCAMode* );
1045 extern PPCInstr* PPCInstr_AvUnary ( PPCAvOp op, HReg dst, HReg src );
1046 extern PPCInstr* PPCInstr_AvBinary ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
1047 extern PPCInstr* PPCInstr_AvBin8x16 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
1048 extern PPCInstr* PPCInstr_AvBin16x8 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
1049 extern PPCInstr* PPCInstr_AvBin32x4 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
1050 extern PPCInstr* PPCInstr_AvBin64x2 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
1051 extern PPCInstr* PPCInstr_AvBin32Fx4 ( PPCAvFpOp op, HReg dst, HReg srcL, HReg srcR );
1052 extern PPCInstr* PPCInstr_AvUn32Fx4 ( PPCAvFpOp op, HReg dst, HReg src );
1053 extern PPCInstr* PPCInstr_AvPerm ( HReg dst, HReg srcL, HReg srcR, HReg ctl );
1054 extern PPCInstr* PPCInstr_AvSel ( HReg ctl, HReg dst, HReg srcL, HReg srcR );
1055 extern PPCInstr* PPCInstr_AvSh ( Bool shLeft, HReg dst, PPCAMode* am_addr );
1056 extern PPCInstr* PPCInstr_AvShlDbl ( UChar shift, HReg dst, HReg srcL, HReg srcR );
1057 extern PPCInstr* PPCInstr_AvSplat ( UChar sz, HReg dst, PPCVI5s* src );
1058 extern PPCInstr* PPCInstr_AvCMov ( PPCCondCode, HReg dst, HReg src );
1059 extern PPCInstr* PPCInstr_AvLdVSCR ( HReg src );
1060 extern PPCInstr* PPCInstr_AvCipherV128Unary ( PPCAvOp op, HReg dst,
1061 HReg srcR );
1062 extern PPCInstr* PPCInstr_AvCipherV128Binary ( PPCAvOp op, HReg dst,
1063 HReg srcL, HReg srcR );
1064 extern PPCInstr* PPCInstr_AvHashV128Binary ( PPCAvOp op, HReg dst,
1065 HReg src, PPCRI* s_field );
1066 extern PPCInstr* PPCInstr_AvBCDV128Trinary ( PPCAvOp op, HReg dst,
1067 HReg src1, HReg src2,
1068 PPCRI* ps );
1069 extern PPCInstr* PPCInstr_Dfp64Unary ( PPCFpOp op, HReg dst, HReg src );
1070 extern PPCInstr* PPCInstr_Dfp64Binary ( PPCFpOp op, HReg dst, HReg srcL,
1071 HReg srcR );
1072 extern PPCInstr* PPCInstr_DfpShift ( PPCFpOp op, HReg dst, HReg src,
1073 PPCRI* shift );
1074 extern PPCInstr* PPCInstr_Dfp128Unary ( PPCFpOp op, HReg dst_hi, HReg dst_lo,
1075 HReg srcR_hi, HReg srcR_lo );
1076 extern PPCInstr* PPCInstr_Dfp128Binary ( PPCFpOp op, HReg dst_hi, HReg dst_lo,
1077 HReg srcR_hi, HReg srcR_lo );
1078 extern PPCInstr* PPCInstr_DfpShift128 ( PPCFpOp op, HReg dst_hi, HReg src_hi,
1079 HReg dst_lo, HReg src_lo,
1080 PPCRI* shift );
1081 extern PPCInstr* PPCInstr_DfpD128toD64 ( PPCFpOp op, HReg dst,
1082 HReg dst_lo, HReg src_lo);
1083 extern PPCInstr* PPCInstr_DfpI64StoD128 ( PPCFpOp op, HReg dst_hi,
1084 HReg dst_lo, HReg src);
1085 extern PPCInstr* PPCInstr_DfpRound ( HReg dst, HReg src, PPCRI* r_rmc );
1086 extern PPCInstr* PPCInstr_DfpRound128 ( HReg dst_hi, HReg dst_lo, HReg src_hi,
1087 HReg src_lo, PPCRI* r_rmc );
1088 extern PPCInstr* PPCInstr_DfpQuantize ( PPCFpOp op, HReg dst, HReg srcL,
1089 HReg srcR, PPCRI* rmc );
1090 extern PPCInstr* PPCInstr_DfpQuantize128 ( PPCFpOp op, HReg dst_hi,
1091 HReg dst_lo,
1092 HReg src_hi,
1093 HReg src_lo, PPCRI* rmc );
1094 extern PPCInstr* PPCInstr_ExtractExpD128 ( PPCFpOp op, HReg dst,
1095 HReg src_hi, HReg src_lo );
1096 extern PPCInstr* PPCInstr_InsertExpD128 ( PPCFpOp op, HReg dst_hi,
1097 HReg dst_lo, HReg srcL,
1098 HReg srcR_hi, HReg srcR_lo );
1099 extern PPCInstr* PPCInstr_Dfp64Cmp ( HReg dst, HReg srcL, HReg srcR );
1100 extern PPCInstr* PPCInstr_Dfp128Cmp ( HReg dst, HReg srcL_hi, HReg srcL_lo,
1101 HReg srcR_hi, HReg srcR_lo );
1102 extern PPCInstr* PPCInstr_EvCheck ( PPCAMode* amCounter,
1103 PPCAMode* amFailAddr );
1104 extern PPCInstr* PPCInstr_ProfInc ( void );
1105
1106 extern void ppPPCInstr(const PPCInstr*, Bool mode64);
1107
1108
1109 /* Some functions that insulate the register allocator from details
1110 of the underlying instruction set. */
1111 extern void getRegUsage_PPCInstr ( HRegUsage*, const PPCInstr*, Bool mode64 );
1112 extern void mapRegs_PPCInstr ( HRegRemap*, PPCInstr* , Bool mode64);
1113 extern Bool isMove_PPCInstr ( const PPCInstr*, HReg*, HReg* );
1114 extern Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc,
1115 UChar* buf, Int nbuf, const PPCInstr* i,
1116 Bool mode64,
1117 VexEndness endness_host,
1118 const void* disp_cp_chain_me_to_slowEP,
1119 const void* disp_cp_chain_me_to_fastEP,
1120 const void* disp_cp_xindir,
1121 const void* disp_cp_xassisted );
1122
1123 extern void genSpill_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
1124 HReg rreg, Int offsetB, Bool mode64 );
1125 extern void genReload_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
1126 HReg rreg, Int offsetB, Bool mode64 );
1127
1128 extern const RRegUniverse* getRRegUniverse_PPC ( Bool mode64 );
1129
1130 extern HInstrArray* iselSB_PPC ( const IRSB*,
1131 VexArch,
1132 const VexArchInfo*,
1133 const VexAbiInfo*,
1134 Int offs_Host_EvC_Counter,
1135 Int offs_Host_EvC_FailAddr,
1136 Bool chainingAllowed,
1137 Bool addProfInc,
1138 Addr max_ga );
1139
1140 /* How big is an event check? This is kind of a kludge because it
1141 depends on the offsets of host_EvC_FAILADDR and
1142 host_EvC_COUNTER. */
1143 extern Int evCheckSzB_PPC (void);
1144
1145 /* Perform a chaining and unchaining of an XDirect jump. */
1146 extern VexInvalRange chainXDirect_PPC ( VexEndness endness_host,
1147 void* place_to_chain,
1148 const void* disp_cp_chain_me_EXPECTED,
1149 const void* place_to_jump_to,
1150 Bool mode64 );
1151
1152 extern VexInvalRange unchainXDirect_PPC ( VexEndness endness_host,
1153 void* place_to_unchain,
1154 const void* place_to_jump_to_EXPECTED,
1155 const void* disp_cp_chain_me,
1156 Bool mode64 );
1157
1158 /* Patch the counter location into an existing ProfInc point. */
1159 extern VexInvalRange patchProfInc_PPC ( VexEndness endness_host,
1160 void* place_to_patch,
1161 const ULong* location_of_counter,
1162 Bool mode64 );
1163
1164
1165 #endif /* ndef __VEX_HOST_PPC_DEFS_H */
1166
1167 /*---------------------------------------------------------------*/
1168 /*--- end host_ppc_defs.h ---*/
1169 /*---------------------------------------------------------------*/
1170