assembler_mips64.cc - OpenGrok cross reference for /art/compiler/utils/mips64/assembler

Lines Matching refs:scratch
2893   Mips64ManagedRegister scratch = mscratch.AsMips64();  in StoreImmediateToFrame()  local
2894   CHECK(scratch.IsGpuRegister()) << scratch;  in StoreImmediateToFrame()
2895   LoadConst32(scratch.AsGpuRegister(), imm);  in StoreImmediateToFrame()
2896   StoreToOffset(kStoreWord, scratch.AsGpuRegister(), SP, dest.Int32Value());  in StoreImmediateToFrame()
2902   Mips64ManagedRegister scratch = mscratch.AsMips64();  in StoreStackOffsetToThread()  local
2903   CHECK(scratch.IsGpuRegister()) << scratch;  in StoreStackOffsetToThread()
2904   Daddiu64(scratch.AsGpuRegister(), SP, fr_offs.Int32Value());  in StoreStackOffsetToThread()
2905   StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value());  in StoreStackOffsetToThread()
2915   Mips64ManagedRegister scratch = mscratch.AsMips64();  in StoreSpanning()  local
2917   LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), SP, in_off.Int32Value());  in StoreSpanning()
2918   StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, dest.Int32Value() + 8);  in StoreSpanning()
2992   Mips64ManagedRegister scratch = mscratch.AsMips64();  in CopyRef()  local
2993   CHECK(scratch.IsGpuRegister()) << scratch;  in CopyRef()
2994   LoadFromOffset(kLoadWord, scratch.AsGpuRegister(), SP, src.Int32Value());  in CopyRef()
2995   StoreToOffset(kStoreWord, scratch.AsGpuRegister(), SP, dest.Int32Value());  in CopyRef()
3001   Mips64ManagedRegister scratch = mscratch.AsMips64();  in CopyRawPtrFromThread()  local
3002   CHECK(scratch.IsGpuRegister()) << scratch;  in CopyRawPtrFromThread()
3003   LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value());  in CopyRawPtrFromThread()
3004   StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, fr_offs.Int32Value());  in CopyRawPtrFromThread()
3010   Mips64ManagedRegister scratch = mscratch.AsMips64();  in CopyRawPtrToThread()  local
3011   CHECK(scratch.IsGpuRegister()) << scratch;  in CopyRawPtrToThread()
3012   LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(),  in CopyRawPtrToThread()
3014   StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(),  in CopyRawPtrToThread()
3020   Mips64ManagedRegister scratch = mscratch.AsMips64();  in Copy()  local
3021   CHECK(scratch.IsGpuRegister()) << scratch;  in Copy()
3024     LoadFromOffset(kLoadWord, scratch.AsGpuRegister(), SP, src.Int32Value());  in Copy()
3025     StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, dest.Int32Value());  in Copy()
3027     LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), SP, src.Int32Value());  in Copy()
3028     StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, dest.Int32Value());  in Copy()
3036   GpuRegister scratch = mscratch.AsMips64().AsGpuRegister();  in Copy()  local
3039     LoadFromOffset(kLoadWord, scratch, src_base.AsMips64().AsGpuRegister(),  in Copy()
3041     StoreToOffset(kStoreDoubleword, scratch, SP, dest.Int32Value());  in Copy()
3043     LoadFromOffset(kLoadDoubleword, scratch, src_base.AsMips64().AsGpuRegister(),  in Copy()
3045     StoreToOffset(kStoreDoubleword, scratch, SP, dest.Int32Value());  in Copy()
3053   GpuRegister scratch = mscratch.AsMips64().AsGpuRegister();  in Copy()  local
3056     LoadFromOffset(kLoadWord, scratch, SP, src.Int32Value());  in Copy()
3057     StoreToOffset(kStoreDoubleword, scratch, dest_base.AsMips64().AsGpuRegister(),  in Copy()
3060     LoadFromOffset(kLoadDoubleword, scratch, SP, src.Int32Value());  in Copy()
3061     StoreToOffset(kStoreDoubleword, scratch, dest_base.AsMips64().AsGpuRegister(),  in Copy()
3079   GpuRegister scratch = mscratch.AsMips64().AsGpuRegister();  in Copy()  local
3082     LoadFromOffset(kLoadWord, scratch, src.AsMips64().AsGpuRegister(), src_offset.Int32Value());  in Copy()
3083 …StoreToOffset(kStoreDoubleword, scratch, dest.AsMips64().AsGpuRegister(), dest_offset.Int32Value()…  in Copy()
3085     LoadFromOffset(kLoadDoubleword, scratch, src.AsMips64().AsGpuRegister(),  in Copy()
3087     StoreToOffset(kStoreDoubleword, scratch, dest.AsMips64().AsGpuRegister(),  in Copy()
3141   Mips64ManagedRegister scratch = mscratch.AsMips64();  in CreateHandleScopeEntry()  local
3142   CHECK(scratch.IsGpuRegister()) << scratch;  in CreateHandleScopeEntry()
3145     LoadFromOffset(kLoadUnsignedWord, scratch.AsGpuRegister(), SP,  in CreateHandleScopeEntry()
3150     Beqzc(scratch.AsGpuRegister(), &null_arg);  in CreateHandleScopeEntry()
3151     Daddiu64(scratch.AsGpuRegister(), SP, handle_scope_offset.Int32Value());  in CreateHandleScopeEntry()
3154     Daddiu64(scratch.AsGpuRegister(), SP, handle_scope_offset.Int32Value());  in CreateHandleScopeEntry()
3156   StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, out_off.Int32Value());  in CreateHandleScopeEntry()
3188   Mips64ManagedRegister scratch = mscratch.AsMips64();  in Call()  local
3190   CHECK(scratch.IsGpuRegister()) << scratch;  in Call()
3191   LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(),  in Call()
3193   Jalr(scratch.AsGpuRegister());  in Call()
3199   Mips64ManagedRegister scratch = mscratch.AsMips64();  in Call()  local
3200   CHECK(scratch.IsGpuRegister()) << scratch;  in Call()
3202   LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(),  in Call()
3204   LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(),  in Call()
3205                  scratch.AsGpuRegister(), offset.Int32Value());  in Call()
3206   Jalr(scratch.AsGpuRegister());  in Call()
3226   Mips64ManagedRegister scratch = mscratch.AsMips64();  in ExceptionPoll()  local
3227   exception_blocks_.emplace_back(scratch, stack_adjust);  in ExceptionPoll()
3229                  scratch.AsGpuRegister(),  in ExceptionPoll()
3232   Bnezc(scratch.AsGpuRegister(), exception_blocks_.back().Entry());  in ExceptionPoll()