Lines Matching refs:r0
27 mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register
28 bic r0, r0, #0x00000002 // disable L2 cache
29 mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register
32 mrc p15, 0, r0, c1, c0, 0
33 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
34 bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */
35 orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
36 orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */
37 mcr p15, 0, r0, c1, c0, 0
40 mrc p15, 0, r0, c1, c0, 2
41 orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)
42 mcr p15, 0, r0, c1, c0, 2
43 mov r0, #0x40000000 // Set EN bit in FPEXC
44 mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly
48 LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base
49 mcr p15, 0, r0, c12, c0, 0
56 str r1, [r0, r2]
73 mov r0,#0x13|0x80|0x40
74 msr CPSR_c,r0
79 LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) /* memory size arg0 */